SEMICONDUCTOR DEVICE

• US 20110101331A1
• Filed: 10/14/2010
• Published: 05/05/2011
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kuwabara, Hideaki, Noda, Kosei, Miyake, Hiroyuki, Takahashi, Kei, Koyama, Jun, Yamazaki, Shunpei, Tsubuku, Masashi, Toyotaka, Kouhei
• Granted Patent: US 8,421,069 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

Claims

1. A semiconductor device comprising an EDMOS circuit comprising:

a first insulating layer over a semiconductor substrate;

a conductive layer over the first insulating layer;

a second insulating layer over the conductive layer;

an oxide semiconductor layer over the second insulating layer, in which a hydrogen concentration is lower than or equal to 5×

10¹⁹ atoms/cm³ and a carrier concentration is lower than or equal to 5×

10¹⁴/cm³;

a source and drain electrode layers over the oxide semiconductor layer;

a gate insulating layer over the oxide semiconductor layer and the source and drain electrode layers; and

a gate electrode layer over the gate insulating layer,

wherein the conductive layer overlaps with the oxide semiconductor layer with the second insulating layer provided therebetween.

2. The semiconductor device according to claim 1, wherein the first insulating layer is a thermally-oxidized layer.

3. The semiconductor device according to claim 1, further comprising a third insulating layer on and in contact with the source electrode layer or the drain electrode layer,

wherein the source electrode layer or the drain electrode layer overlaps with part of the gate electrode layer with the gate insulating layer and the third insulating layer provided therebetween.

4. A semiconductor device according to claim 1, wherein the semiconductor device is a CPU.

5. A semiconductor device according to claim 1, wherein the semiconductor device is an LSI.

6. A semiconductor device according to claim 1, wherein the semiconductor device is a DRAM.

7. A semiconductor device comprising an EDMOS circuit comprising:

a first transistor comprising a first oxide semiconductor layer and a second transistor comprising a second oxide semiconductor layer over a semiconductor substrate,

wherein a hydrogen concentration is lower than or equal to 5×

10¹⁹ atoms/cm³ and a carrier concentration is lower than or equal to 5×

10¹⁴/cm³ in each of the first oxide semiconductor layer and the second oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein an oxide semiconductor layer which is a resistor is provided over the same substrate, between a first conductive layer and a second conductive layer which overlaps with the first conductive layer.

9. The semiconductor device according to claim 7, wherein an off-current value of the transistor is less than or equal to 1×

10<sup>−

13</sup> A.