SEMICONDUCTOR DEVICE

• US 20110101351A1
• Filed: 10/27/2010
• Published: 05/05/2011
• Est. Priority Date: 10/29/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 10,490,553 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/46 Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 manufacture of electrodes thereon H01L21/44
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

Claims

1. A semiconductor device comprising a memory cell, the memory cell comprising:

a first transistor comprising a first gate electrode, the first gate electrode being formed over a substrate; and

a second transistor over the substrate, the second transistor comprising a second source electrode and a second drain electrode,

wherein the second transistor includes an oxide semiconductor layer, and

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

2. The semiconductor device according to claim 1,

wherein the substrate comprises a semiconductor material.

3. The semiconductor device according to claim 1,

wherein the substrate is an SOI substrate.

4. The semiconductor device according to claim 1,

wherein the substrate is a single crystal semiconductor substrate.

5. The semiconductor device according to claim 1,

wherein the first transistor comprises a channel formation region in the substrate.

6. The semiconductor device according to claim 1,

wherein the first transistor comprises a channel formation region comprising silicon.

7. The semiconductor device according to claim 1, further comprising an insulating layer over the first transistor,

wherein the second transistor is provided over the insulating layer.

8. The semiconductor device according to claim 1, further comprising an insulating layer over the first transistor,

wherein the second transistor is provided over the insulating layer, and

wherein the second transistor overlaps with the first transistor.

9. The semiconductor device according to claim 1, further comprising a capacitor electrically connected to the first gate electrode.

10. A semiconductor device comprising a memory cell, the memory cell comprising:

a first transistor comprising a first gate electrode, the first gate electrode being formed over a substrate; and

a second transistor over the substrate, the second transistor comprising;

a second gate electrode;

a gate insulating layer over the second gate electrode;

an oxide semiconductor layer over the gate insulating layer; and

a second source electrode and a second drain electrode over the gate insulating layer,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

11. The semiconductor device according to claim 10,

wherein the substrate comprises a semiconductor material.

12. The semiconductor device according to claim 10,

wherein the substrate is an SOI substrate.

13. The semiconductor device according to claim 10,

wherein the substrate is a single crystal semiconductor substrate.

14. The semiconductor device according to claim 10,

wherein the first transistor comprises a channel formation region in the substrate.

15. The semiconductor device according to claim 10,

wherein the first transistor comprises a channel formation region comprising silicon.

16. The semiconductor device according to claim 10, further comprising an insulating layer over the first transistor,

wherein the second transistor is provided over the insulating layer.

17. The semiconductor device according to claim 10, further comprising an insulating layer over the first transistor,

wherein the second transistor is provided over the insulating layer, and

wherein the second transistor overlaps with the first transistor.

18. The semiconductor device according to claim 10, further comprising a capacitor electrically connected to the first gate electrode.

19. The semiconductor device according to claim 10, further comprising a protective insulating layer over and in contact with the oxide semiconductor layer.

20. The semiconductor device according to claim 10,

wherein a top surface of the oxide semiconductor layer is in contact with the second source electrode and the second drain electrode.

21. The semiconductor device according to claim 10,

wherein a bottom surface of the oxide semiconductor layer is in contact with the second source electrode and the second drain electrode.

22. A semiconductor device comprising a memory cell, the memory cell comprising:

a first transistor comprising a first gate electrode, the first gate electrode being formed over a substrate;

an interlayer insulating layer over the first transistor; and

a second transistor comprising;

an oxide semiconductor layer over the interlayer insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a second gate electrode over the gate insulating layer; and

a second source electrode and a second drain electrode over the interlayer insulating layer,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

23. The semiconductor device according to claim 22,

wherein the substrate comprises a semiconductor material.

24. The semiconductor device according to claim 22,

wherein the substrate is an SOI substrate.

25. The semiconductor device according to claim 22,

wherein the substrate is a single crystal semiconductor substrate.

26. The semiconductor device according to claim 22,

wherein the first transistor comprises a channel formation region in the substrate.

27. The semiconductor device according to claim 22,

wherein the first transistor comprises a channel formation region comprising silicon.

28. The semiconductor device according to claim 22,

wherein the second transistor overlaps with the first transistor.

29. The semiconductor device according to claim 22,

wherein the second source electrode and the second drain electrode are interposed between the interlayer insulating layer and the oxide semiconductor layer.

30. The semiconductor device according to claim 22,

wherein a top surface of the oxide semiconductor layer is in contact with the second source electrode and the second drain electrode.

31. The semiconductor device according to claim 22,

wherein a bottom surface of the oxide semiconductor layer is in contact with the second source electrode and the second drain electrode.

32. The semiconductor device according to claim 22, further comprising a capacitor electrically connected to the first gate electrode.