Stress Memorization Technique Using Silicon Spacer

• US 20110101506A1
• Filed: 10/29/2009
• Published: 05/05/2011
• Est. Priority Date: 10/29/2009
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Robison, Robert R., Butt, Shahid A., Ontalus, Viorel
• Application Number:
  US12/608,107
• Publication Number:
  US 20110101506A1
• Time in Patent Office: Days
• US Class Current: 257/632
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process.

Claims

1. A structure for memorizing tensile stress in a semiconductor device, comprising:

a gate electrode of the semiconductor device;

a silicon spacer adjacent to the gate electrode; and

a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process.

2. The structure of claim 1, further comprising a channel region of the semiconductor device.

3. The structure of claim 2, wherein a tensile stress is memorized by the channel region during the annealing process.

4. The structure of claim 1, wherein the silicon spacer comprises polycrystalline silicon.

5. The structure of claim 1, wherein the silicon spacer comprises amorphous silicon.

6. The structure of claim 1, wherein the capping layer comprises nitride.

7. The structure of claim 1, wherein the capping layer comprises oxide.

8. A method for memorizing tensile stress in a semiconductor device, the method comprising:

forming a silicon spacer adjacent to a gate electrode of the semiconductor device;

forming a capping layer over the silicon spacer and the gate electrode; and

annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing.

9. The method of claim 8, further comprising memorizing a tensile stress in a channel region of the semiconductor device during annealing.

10. The method of claim 8, wherein the silicon spacer comprises polycrystalline silicon.

11. The method of claim 8, wherein the silicon spacer comprises amorphous silicon.

12. The method of claim 8, wherein the capping layer comprises nitride.

13. The method of claim 8, wherein the capping layer comprises oxide.

14. The method of claim 8, further comprising removing the capping layer after annealing.

15. The method of claim 14, further comprising removing the silicon spacer.

16. The method of claim 15, further comprising replacing the silicon spacer with a second spacer.

17. The method of claim 17, wherein the second spacer comprises nitride.

18. The method of claim 17, wherein the second spacer comprises oxide.

19. A disposable silicon spacer, the disposable silicon spacer configured to induce a tensile stress in a semiconductor device during a stress memorization technique (SMT) process.

20. The disposable silicon spacer of claim 19, wherein the disposable silicon spacer is located adjacent to a gate electrode of the semiconductor device.