ADAPTIVE-GAIN STEP-UP/DOWN SWITCHED-CAPACITOR DC/DC CONVERTERS

• US 20110101938A1
• Filed: 11/20/2008
• Published: 05/05/2011
• Est. Priority Date: 11/21/2007
• Status: Abandoned Application

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Ma, Dongsheng, Chowdhury, Inshad
• Application Number:
  US12/744,011
• Publication Number:
  US 20110101938A1
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A switched-capacitor DC-DC converter has a reconfigurable power stage with variable gain ratio and/or interleaving regulation for low ripple voltage, fast load transient operation, variable output voltage and high efficiency. Since the power stage has multiple switches per capacitor, the converter exploits reconfigurable characteristics of the power stage for fast dynamic control and adaptive pulse control for tight and efficient voltage regulation.

Claims

1. A DC-DC converter comprising:

(a) a voltage input;

(b) a voltage output;

(c) a ground;

(d) an output capacitor connected between the voltage output and the ground;

(e) a plurality of capacitors each having a top plate and bottom plate;

(f) for each of the capacitors;

(i) a first switch connected between the top plate of the capacitor and the voltage input;

(ii) a second switch connected between the top plate of the capacitor and the voltage output;

(iii) at least one of;

(A) a third switch connected between the voltage input and the bottom plate of the capacitor;

(B) a fourth switch connected between the bottom plate of the capacitor and the voltage output;

(iv) a fifth switch connected between the bottom plate of the capacitor and the ground; and

(v) a sixth switch connected between the top plate of the capacitor and the bottom plate of an another one of the plurality of capacitors such that each of the plurality of capacitors is connected to an adjacent one of the plurality of capacitors and such that a first one and a last one of the plurality of capacitors are connected; and

(g) a circuit for controlling the first through sixth switches for each of the plurality of capacitors in a plurality of clock phases such that during each of the clock phases, one of the plurality of capacitors is discharged at the voltage output while at least one other of the plurality of capacitors is charged from the voltage input, wherein the plurality of clock phases do not overlap.

2. The DC-DC converter of claim 1, wherein the circuit controls the first through sixth switches to select one of a plurality of voltage gains.

3. The DC-DC converter of claim 1, comprising at least three of said plurality of capacitors.

4. The DC-DC converter of claim 3, wherein the circuit controls the first through sixth switches to select one of a plurality of voltage gains.

5. The DC-DC converter of claim 4, wherein the at least three capacitors comprise first, second and third capacitors, and wherein:

for a gain ratio of 1/3, the first and second capacitors are connected in series between the voltage input and the voltage output, and the third capacitor is connected between the second capacitor and the ground;

for a gain ratio of 1/2, the first and second capacitors are connected between the voltage input and the ground, and the third capacitor is connected between the voltage output and the ground;

for a gain ratio of 2/3, the first capacitor is connected between the voltage input and the voltage output, and the second and third capacitors are connected in series between the first capacitor and the ground;

for a gain ratio of 1, the first and second capacitors are connected in parallel between the voltage input and the ground, and the third capacitor is connected between the voltage output and the ground;

for a gain ratio of 3/2, the first and second capacitors are connected in series between the voltage input and the ground, and the third capacitor is connected between the voltage input and the voltage output;

for a gain ratio of 2, the first and second capacitors are connected in parallel between the voltage input and the ground, and the third capacitor is connected between the first capacitor and the voltage output; and

for a gain ratio of 3, the first and second capacitors are connected in series between the voltage input and the ground, and the third capacitor is connected between the first capacitor and the voltage output.

6. The DC-DC converter of claim 1, further comprising an analog-to-digital converter connected to the voltage output.

7. The DC-DC converter of claim 6, wherein the analog-to-digital converter is a ring oscillator based analog-to-digital converter.

8. The DC-DC converter of claim 7, wherein the ring oscillator based analog-to-digital converter comprises:

a NOR gate;

a plurality of delay cells connected in series with an output of the NOR gate;

a feedback loop from an output of last one of the delay cells to the NOR gate; and

a pulse counter connected to the output of the last one of the delay cells;

wherein the NOR gate and the plurality of delay cells are powered from the voltage output.

9. The DC-DC converter of claim 1, wherein the circuit for controlling dynamically controls the switches.

10. An analog-to-digital converter for converting an analog signal to a digital signal, the analog-to-digital converter comprising:

a NOR gate;

a plurality of delay cells connected in series with an output of the NOR gate;

a feedback loop from an output of last one of the delay cells to the NOR gate; and

a pulse counter connected to the output of the last one of the delay cells;

wherein the NOR gate and the plurality of delay cells are powered by the analog signal.

11. A method for DC-DC conversion, the method comprising:

providing a DC-DC converter comprising;

(a) a voltage input;

(b) a voltage output;

(c) a ground;

(d) an output capacitor connected between the voltage output and the ground;

(e) a plurality of capacitors each having a top plate and bottom plate;

(f) for each of the capacitors;

(i) a first switch connected between the top plate of the capacitor and the voltage input;

(ii) a second switch connected between the top plate of the capacitor and the voltage output;

(iii) at least one of;

(A) a third switch connected between the voltage input and the bottom plate of the capacitor;

(B) a fourth switch connected between the bottom plate of the capacitor and the voltage output;

(iv) a fifth switch connected between the bottom plate of the capacitor and the ground; and

(v) a sixth switch connected between the top plate of the capacitor and the bottom plate of an another one of the plurality of capacitors such that each of the plurality of capacitors is connected to an adjacent one of the plurality of capacitors and such that a first one and a last one of the plurality of capacitors are connected; and

(g) a circuit for controlling the first through sixth switches for each of the plurality of capacitors in a plurality of clock phases such that during each of the clock phases, one of the plurality of capacitors is discharged at the voltage output while at least one other of the plurality of capacitors is charged from the voltage input, wherein the plurality of clock phases do not overlap;

controlling the switches, by use of the circuit for controlling, to select a gain ratio; and

operating the DC-DC converter to operate at the gain ratio selected.

12. The method of claim 11, wherein the DC-DC converter comprises at least three of said plurality of capacitors.

13. The method of claim 12, wherein the at least three capacitors comprise first, second and third capacitors, and wherein:

for a gain ratio of 1/3, the first and second capacitors are connected in series between the voltage input and the voltage output, and the third capacitor is connected between the second capacitor and the ground;

for a gain ratio of 1/2, the first and second capacitors are connected between the voltage input and the ground, and the third capacitor is connected between the voltage output and the ground;

for a gain ratio of 213, the first capacitor is connected between the voltage input and the voltage output, and the second and third capacitors are connected in series between the first capacitor and the ground;

for a gain ratio of 1, the first and second capacitors are connected in parallel between the voltage input and the ground, and the third capacitor is connected between the voltage output and the ground;

for a gain ratio of 3/2, the first and second capacitors are connected in series between the voltage input and the ground, and the third capacitor is connected between the voltage input and the voltage output;

for a gain ratio of 2, the first and second capacitors are connected in parallel between the voltage input and the ground, and the third capacitor is connected between the first capacitor and the voltage output; and

for a gain ratio of 3, the first and second capacitors are connected in series between the voltage input and the ground, and the third capacitor is connected between the first capacitor and the voltage output.

14. The method of claim 11, wherein the step of controlling is performed dynamically.