LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE
First Claim
1. A logic circuit including a first period during which a clock signal is input and a second period during which the clock signal is not input, comprising:
- a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×
1019 (atoms/cm3) or lower.
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Accused Products
Abstract
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
161 Citations
18 Claims
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1. A logic circuit including a first period during which a clock signal is input and a second period during which the clock signal is not input, comprising:
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a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period, wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×
1019 (atoms/cm3) or lower. - View Dependent Claims (2)
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3. A logic circuit including a first period during which an enable signal is at a high level and a second period during which the enable signal is at a low level, comprising:
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an AND gate, wherein a first input terminal of the AND gate is electrically connected to an enable signal line, and a second input terminal of the AND gate is electrically connected to a clock signal line; and a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the AND gate, wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period, and wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×
1019 (atoms/cm3) or lower. - View Dependent Claims (4, 5, 6, 7)
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8. A logic circuit including a first period during which an enable signal is at a low level and a second period during which the enable signal is at a high level, comprising:
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a NOR gate, wherein a first input terminal of the NOR gate is electrically connected to an enable signal line, and a second input terminal of the NOR gate is electrically connected to an inverted clock signal line; and a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the NOR gate, wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period, and wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×
1019 (atoms/cm3) or lower. - View Dependent Claims (9, 10, 11, 12)
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13. A logic circuit including a first period during which an enable signal is at a high level and a second period during which the enable signal is at a low level, comprising:
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a latch, wherein a first input terminal of the latch is electrically connected to an enable signal line, and a second input terminal of the latch is electrically connected to an inverted clock signal line; and a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the latch, wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal, and wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×
1019 (atoms/cm3) or lower. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification