DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS

• US 20110102029A1
• Filed: 01/07/2011
• Published: 05/05/2011
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: GOMM, TYLER
• Granted Patent: US 8,149,034 B2
• Time in Patent Office: Days
• US Class Current: 327/149
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.

Claims

1. A delay circuit, comprising:

a delay line comprising a plurality of inverting delay devices coupled to each other in series from a first inverting delay device to a last inverting delay device, the first inverting delay device having an input receiving a reference clock signal; and

an exit tree coupled to the delay line, the exit tree comprising;

a plurality of first logic devices each of which has a first input coupled to a respective one of the inverting delay devices and a second input coupled to receive a respective enable signal; and

a pair of second logic devices each of which has a plurality of input terminals coupled to respective outputs of a plurality of the first logic devices that are coupled to alternating ones of the inverting delay devices, one of the second logic devices being coupled to the outputs of the first logic devices that are different from the outputs of the first logic devices to which the other of the first logic devices are coupled.

2. The delay circuit of claim 1, further comprising a phase mixer having first and second inputs coupled to outputs of respective ones of the second logic devices, the phase mixer being operable to generate a clock output signal having a timing that is interpolated between the timing of a signal applied to the first input and the timing of a signal applied to the second input.

3. The delay circuit of claim 1 wherein the first and second logic devices comprise respective NAND gates.

4. The delay circuit of claim 1 wherein the inverting delay devices comprise respective inverting logic gates.

5. The delay circuit of claim 1 wherein the inverting delay devices comprise respective inverters.

6. A phase inverter, comprising:

an odd number of first inverters coupled in series between a first input and a first output, the first inverters having a collective propagation delay from the first input to the first output that is equal to a first delay value; and

an even number of second inverters coupled in series between a second input and a second output, the second input being isolated from the first input, the second inverters having a collective propagation delay from the second input to the second output that is equal to a second delay value, the second delay value being substantially equal to the first delay value.

7. The phase inverter of claim 6 wherein the first inverters each have an input impedance that is different from an input impedance of the second inverters, and wherein the phase inverter further comprises:

a first inverter having an input coupled to the second input; and

a second inverter having an input coupled to the first input.

8. The phase inverter of claim 6, further comprising a phase mixer having first and second inputs coupled to the first and second outputs of the first and second inverters, respectively, the phase mixer being operable to generate a clock output signal having a timing that is interpolated between the timing of a signal applied to the first input of the phase mixer and the timing of a signal applied to the second input of the phase mixer.

9. A method of delaying a reference clock signal, comprising:

generating a plurality of delayed signals each of which is delayed relative to another one of the delayed signals by a coarse delay interval, the delayed signals having delays differing from each other by one coarse delay interval being inverted from each other;

selecting one of the delayed signals and applying the selected delayed signal to a first output;

inverting another one of the delayed signals having a delay differing from the delay of the selected delayed signal by a single coarse delay interval; and

applying the inverted delayed signal to a second output.

10. The method of claim 9 wherein the selected delayed signal is applied to the first output with a propagation delay that is substantially equal to a propagation delay at which the other one of the delayed signals is applied to the second output.

11. The method of claim 9 wherein the delayed signals are generated by respective series coupled inverting delay devices, and wherein the method further comprises disabling inverting delay devices downstream from the inverting delay device generating the selected delayed signal.

12. A method of synchronizing an output clock signal to a reference clock signal, comprising:

sequentially inverting and delaying the reference clock signal by a sequence of coarse delays so that a plurality of delayed signals are generated each of which is inverted and delayed from a prior delayed signal by one coarse delay;

selecting two of the delayed signals, the selected delayed signals having respective delays that differ from each other by one coarse delay;

inverting one of the selected delayed signals without inverting the other of the selected signals;

using the selected delayed signals and an interpolation value to interpolate between the delay of the inverted delayed signal and the delay of the other one of the delayed signal to provide an output clock signal; and

comparing the timing of the reference clock signal to the timing of the output clock signal to determine the selected delayed signals and the interpolation value.

13. The method of claim 12 wherein the delay of the inverted delayed signal differs from the delay of the other of the delayed signals by substantially one coarse delay.

14. The method of claim 12 wherein the delayed signals are generated by respective series coupled inverting delay devices, and wherein the method further comprises disabling inverting delay devices downstream from the inverting delay device generating the selected delayed signal.