LOOP FILTER

• US 20110102032A1
• Filed: 10/29/2009
• Published: 05/05/2011
• Est. Priority Date: 10/29/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics Design and Application GmbH (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Application GmbH (STMicroelectronics NV)
• Inventors: Zeller, Sebastian
• Granted Patent: US 8,248,123 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node. such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

Claims

1. A loop filter, comprising

a first node to receive an input signal to the loop filter, and a second node to provide an output signal of the loop filter;

a cascade arrangement of at least a first circuit for generating a zero, a second circuit for generating a first pole, and a third circuit for generating a second pole to form a passive loop filter of at least a 3rd order, the cascade arrangement comprising at least a first signal path coupled between the first node and the second node;

wherein the cascade arrangement is coupled between the first node and the second node such that the first circuit for generating a zero is coupled to the first node through the second circuit for generating the first pole and the third circuit for generating the second pole;

at least one transistor circuit; and

a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

2. The loop filter of claim 1 wherein the impedance of the first circuit is lower than the impedance of the second and third circuits.

3. The loop filter of claim 1 wherein the first circuit for generating a zero comprises at least a resistor and a capacitor.

4. The loop filter of claim 3 wherein the resistor and the capacitor are coupled in series between the second node and a reference node.

5. The loop filter of claim 1 wherein the third circuit is coupled in the first signal path and comprises at least a resistor and a capacitor, with the capacitor coupled between the first signal path and a reference node and the resistor coupled in the signal path between the first circuit and the first node.

6. The loop filter of claim 1, further comprising:

an n-th circuit for generating an additional pole coupled in the first signal path and comprising at least a resistor and a capacitor, with the capacitor coupled between the first signal path and a reference node and the resistor coupled in the signal path between the third circuit and the first node.

7. The loop filter of claim 1 wherein the second and third circuits are configured such that the input impedance of the second pole is higher than the output impedance of the first pole.

8. The loop filter of claim 1 wherein the transistor circuit comprises at least a first transistor having a control node and a controlled path, with the control node of the first transistor coupled to the second signal path and the controlled path of the first transistor coupled to the second node.

9. The loop filter of claim 8 wherein the transistor circuit comprises at least a second transistor having a control node and a controlled path, with the control node of the second transistor coupled to the second signal path and the controlled path of the second transistor coupled to the second node, wherein the first and second transistors are of opposite conductive types.

10. The loop filter of claim 1, further comprising:

a resistor coupled between the transistor circuit and the second node.

11. A loop filter, comprising:

a first node to receive an input signal to the loop filter, and a second node to provide an output signal of the loop filter;

a cascade arrangement of at least a first circuit to generate a zero, a second circuit to generate a first pole, and a third circuit to generate a second pole to form a passive loop filter of at least 3rd order, the cascade arrangement comprising a first signal path coupled between the first node and the second node;

wherein the first circuit to generate a zero comprises at least a first resistor and a first capacitor coupled in series between the second node and a reference node;

wherein the second circuit is coupled to the first signal path and comprises at least a second capacitor coupled between the first signal path and a reference node;

wherein the third circuit is coupled to the first signal path and comprises a third resistor and a third capacitor, with the third capacitor coupled between the first signal path and a reference node and the third resistor coupled in the first signal path;

wherein the cascade arrangement is coupled between the first node and the second node such that the first circuit for generating a zero is coupled to the first node through the second circuit to generate the first pole and the third circuit to generate the second pole;

at least one transistor circuit; and

a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

12. The loop filter of claim 11, further comprising a fourth resistor coupled between the second node and the at least one transistor circuit.

13. The loop filter of claim 12 wherein the at least one transistor circuit comprises a pair of transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to the fourth resistor.

14. A circuit, comprising:

a loop filter, the loop filter comprising a first node to receive an input signal to the loop filter and a second node to provide an output signal of the loop filter;

a first resistor and first capacitor series coupled between the second node and a reference node;

a first circuit to generate a first pole, the first circuit comprising a second capacitor coupled between the second node and the reference node and the first resistor; and

a second circuit for generating a second pole comprising a second resistor having a first terminal coupled to the second node and a second terminal coupled to a first terminal of a third capacitor, the third capacitor having a second terminal coupled to the reference node, and the second terminal of the second resistor coupled to the first node.

15. The circuit of claim 14, comprising at least one transistor circuit having first and second transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to a first terminal of a fourth transistor that has its second terminal coupled to the second node, and a first one of the two transistors having a second conduction terminal coupled to a voltage source and the other one of the pair of transistors having a second conduction terminal coupled to the reference node.

16. The circuit of claim 15, further comprising a charge pump having an input coupled to the second node of the loop filter and first and second outputs coupled to first and second inputs of a phase detector circuit that has a first output coupled to an input of a divider that has an output coupled to an input of a voltage controlled oscillator that has an output coupled to the first node of the loop filter.

17. A phase-locked loop, comprising:

a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator, wherein the loop filter comprises;

a first node to provide an input signal to the loop filter, and a second node to provide an output signal of the loop filter;

a cascade arrangement of at least a first circuit to generate a zero, a second circuit to generate a first pole and a third circuit to generate a second pole to form a passive loop filter of at least 3rd order, the cascade arrangement comprising a first signal path coupled between the first node and the second node;

wherein the cascade arrangement is coupled between the first node and the second node such that the first circuit to generate a zero is coupled to the first node through the second circuit to generate the first pole and the third circuit to generate the second pole;

at least one transistor circuit; and

a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

18. The phase-locked loop of claim 17 wherein the at least one transistor circuit comprises a pair of transistors, each transistor having a gate terminal coupled to the second signal path and a conduction terminal coupled to a first terminal of a first resistor having a second terminal coupled to the second node.

19. The phase-locked loop of claim 18 wherein the first circuit comprises at least a second resistor and a first capacitor coupled in series between the second node and a reference node, and the second circuit comprises at least a second capacitor coupled between the second node and the reference node and a third resistor having a first terminal coupled to the second node and a second terminal, and the third circuit comprises a third capacitor having a first terminal coupled to the second terminal of the third resistor and a second terminal coupled to the reference node and a fourth resistor having a first terminal coupled to the first terminal of the third capacitor and a second terminal coupled to the first node.