APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

• US 20110102042A1
• Filed: 01/08/2011
• Published: 05/05/2011
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Oldiges, Philip J., Cannon, Ethan H., Warnock, James D., Wendel, Dieter, Ning, Tak H., Muller, K. Paul, Sigal, Leon J., KleinOsowski, AJ
• Granted Patent: US 8,354,858 B2
• Time in Patent Office: Days
• US Class Current: 327/199
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356156 with synchronous operation

Abstract

A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Claims

1-9. -9. (canceled)

10. A circuit, comprising:

at least one hardened, series transistor; and

at least one non-hardened transistor.

11. The circuit according to claim 10, wherein the circuit is a latch.

12. The circuit according to claim 11, wherein the at least one non-hardened transistor includes one or more transistors having only a gate terminal connected to a storage node of the latch.

13. The circuit according to claim 12, wherein the at least one non-hardened transistor includes one or more transistors that remain ON upon both ofthe latch holding its state, and a respective storage node at logic state 0, andthe latch holding its state, and the respective storage node at logic state 1.

14. The circuit according to claim 12, wherein the circuit further includes a multiplexer circuit, and the at least one non-hardened transistor includes a transistor in the latch that is directly connected to a data node, which is directly connected to the multiplexer circuit.

15. The circuit according to claim 12, wherein the at least one non-hardened transistor includes a transistor always driven ON during a default state of the latch.

16. The circuit according to claim 11, wherein the at least one hardened transistor only includes transistors that are part of a cross-coupled inverter of the latch.

17. The circuit according to claim 11, wherein a hardened, series transistor is located in all SEU-susceptible transistor nodes of the circuit.

18. The circuit according to claim 11, wherein the circuit includes a master latch and a slave latch, and the at least one non-hardened transistor includes a transistor in the slave latch that is directly connected to a data node, which is directly connected to the master latch.

19. The circuit according to claim 11, wherein the transistor is an SOI device.

20. The circuit according to claim 11, wherein the hardened, series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.