SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF COMPONENTS IN A MULTICHIP MEMORY MODULE

• US 20110103122A1
• Filed: 01/07/2011
• Published: 05/05/2011
• Est. Priority Date: 04/08/2004
• Status: Active Grant

• Current Assignee: Jeffery W. Janzen
• Original Assignee: Jeffery W. Janzen
• Inventors: Janzen, Jeffery W.
• Granted Patent: US 8,438,329 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

Claims

1. A memory module comprising;

a circuit board;

a memory hub positioned in approximately a center of the circuit board;

a plurality of memory devices positioned around the memory hub and arranged in pairs, each memory device including pins associated with a first functional group of signals adjacent a first end of the device and pins associated with a second functional group of signals adjacent a second end of the device, and the first ends of the devices in each pair being positioned adjacent one another on the circuit board and the second end of each device in a pair being positioned adjacent a second end of a device in one of the other pairs; and

an edge connector positioned along an edge of the circuit board and coupled to the memory hub.

2. The memory module of claim 1 where the electrical contacts are pins.

3. The memory module of claim 1 wherein the memory devices of the pairs are arranged orthogonally relative to one another.

4. The memory module of claim 1 wherein the memory devices of the pairs are arranged parallel relative to one another.

5. The memory module of claim 1 wherein the pairs of memory devices are positioned orthogonally relative to the other pairs of memory devices.

6. The memory module of claim 1 wherein each memory device of a pair is oriented 180 degrees relative to the other memory device.

7. The memory module of claim 1 wherein each of the plurality of memory devices comprises a wide data memory device.

8. The memory module of claim 1 wherein each the plurality of memory devices comprises a low-width memory device.

9. A multi-chip memory module comprising:

a memory hub;

a plurality of memory devices positioned around the memory hub, arranged in pairs, and coupled to the memory hub, each respective one of the memory devices including electrical contacts associated with a first functional group of signals adjacent a first end of the respective memory device and electrical contacts associated with a second functional group of signals adjacent a second end of the respective memory device, and the first end of each memory device in each pair being positioned adjacent one another and the second end of each device in a pair being positioned adjacent a second end of a device in one of the other pairs.

10. The multi-chip memory module of claim 9, further comprising a first bus coupled to the memory hub and to the electrical contacts associated with the first functional group of signals of a memory device of a pair and further comprising a second bus coupled to the memory hub and to the electrical contacts associated with the second functional group of signals of the same memory device of the same pair, the second bus further coupled to the electrical contacts associated with the second functional group of signals for a memory device of another pair.

11. The multi-chip memory module of claim 10 wherein first and second busses are oriented at an angle relative to one another.

12. The multi-chip memory module of claim 9, further comprising first busses coupled to the electrical contacts associated with the first functional group of signals of the plurality of memory devices and further comprising second busses coupled to the electrical contacts associated with the second functional group of signals of the plurality of memory devices, the first busses coupled to memory devices of two different pairs and each of the second busses coupled to a respective one of the plurality of memory devices.

13. The multi-chip memory module of claim 9 wherein the electrical contacts associated with the first functional group of signals comprises electrical contacts configured to receive command and address signals.

14. The multi-chip memory module of claim 9 wherein the electrical contacts associated with the second functional group of signals comprises electrical contacts configured to receive data signals.

15. A multi-chip memory module comprising:

a circuit board;

a memory hub on the circuit board; and

a plurality of memory devices coupled to the memory hub, wherein pairs of the memory devices are positioned around the memory hub, each respective one of the memory devices in a respective pair being physically rotated 180 degrees in a plane of the circuit board relative to the other device in the pair.

16. The multi-chip memory module of claim 15 wherein the circuit board comprises a first side and a second side opposite of the first side, and memory devices are located on both the first and second sides of the circuit board.

17. The multi-chip memory module of claim 15 wherein the circuit board comprises a first edge and a first edge connector formed at the first edge.

18. The multi-chip memory module of claim 17 wherein the circuit board further comprises a second edge opposite the first edge, the circuit board further including a second edge connector formed at the second edge.

19. The multi-chip memory module of claim 15 wherein the memory hub is position substantially at a middle of the circuit board.

20. The multi-chip memory module of claim 15 wherein the circuit board comprises busses electrically coupled to the memory hub, the busses formed on the circuit board routed through a region covered by a memory device.

21. The multi-chip memory module of claim 15 wherein the circuit board comprises an edge and further comprises a bus electrically coupled to the memory hub, at least a portion of the bus formed at an angle relative to the edge.