GPS-BASED MULTI-MODE SYNCHRONIZATION AND CLOCKING FEMTO-CELLS, PICO-CELLS AND MACRO BASE STATIONS

• US 20110103337A1
• Filed: 05/01/2009
• Published: 05/05/2011
• Est. Priority Date: 05/01/2008
• Status: Abandoned Application

• Current Assignee: U-Blox AG (u-blox Holding AG)
• Original Assignee: U-Blox AG (u-blox Holding AG)
• Inventors: Bryant, Roderick, Glennon, Eamonn P.
• Application Number:
  US12/990,350
• Publication Number:
  US 20110103337A1
• Time in Patent Office: Days
• US Class Current: 370/329
• CPC Class Codes: G04G 7/02 by radio
• CPC Class Codes: H03J 1/0008 using a central processing unit, e.g. a microprocessor digital tuning in general H03J5/0245
• CPC Class Codes: H03J 7/04 where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H04J 3/0644 External master-clock
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master

Abstract

A method is disclosed for providing syntonisation, synchronization, position or some combination to a wireless base station, micro-cell, pico-cell, femto-cell or access point, by providing holdover backup in a GPS clock module via at least one interface between the GPS clock module and an external time or frequency reference. Switching between synchronization modes is designed to occur on the control side of the oscillator portion of the module rather than at the output of two oscillators. A corresponding GPS clock module apparatus is disclosed for providing holdover backup via at least one interface between the GPS clock module and external time or frequency references.

Claims

1. A method comprising providing holdover backup in a GPS clock module used to provide syntonisation, synchronization, position or some combination to a wireless base station, micro-cell, pico-cell, femto-cell or access point, via at least one interface between the GPS clock module and external time or frequency references.

2. The method of claim 1 comprising informing the GPS clock module over a serial interface of errors in the GPS clock module time or frequency based on measurements made externally.

3. The method of claim 1 in which the GPS clock module estimates the precise time or precise period associated with edges of an externally generated timing or frequency reference while fixing and using the estimated times of the edges or the periods between them to maintain estimates of time and frequency during holdover.

4. The method of claim 3 further comprising deriving the said externally generated frequency reference by dividing a reference frequency from a reference oscillator.

5. The method of claim 4 further comprising interfacing a temperature sensor to the GPS clock module, characterizing the temperature characteristics of the oscillator by the GPS clock module and compensating for those characteristics during holdover.

6. The method of claim 4 comprising controlling or disciplining the said external reference oscillator using an output interface to the GPS clock module so as to set its frequency error closely to zero.

7. The method of claim 3 comprising deriving the said externally generated frequency reference from an SDH link.

8. The method of claim 3 comprising generating by an external GPS receiver the said externally generated timing reference.

9. The method of claim 3 comprising deriving the said externally generated timing reference from an SDH link.

10. The method of claim 3 further comprising switching between external timing or frequency references by use of one or more additional interfaces to the GPS clock module.

11. The method of claim 1 further comprising processing the externally derived frequency and/or time synchronization error estimates by using a separate synch controller firmware routine and switching oscillator control from the GPS synch controller to the external synch controller during holdover.

12. The method of claim 11 further comprising deriving said frequency error estimates from a sequence of time error estimates.

13. The method of claim 11 further comprising supplying the external synch controller with temperature estimates for use in frequency compensation of the internal oscillator.

14. The method of claim 1 further comprising using a single multi-mode synch controller firmware routine to process frequency and time error estimates from a GPS time filter and frequency and/or time synchronization error estimates obtained via external interfaces and controlling the internal oscillator based on a combination of error the said estimates.

15. The method of claim 14 further comprising deriving from a sequence of time error estimates said frequency error estimates obtained via external interfaces.

16. The method of claim 14 further comprising supplying the said multi-mode synch controller with temperature estimates for use in frequency compensation of the internal oscillator.

17. The method of claim 1 further comprises using a single multi-mode time filter to processes GPS measurements and frequency and/or time synchronization error estimates obtained via external interfaces to estimate time and frequency error based on a combination of all available measurements and error estimates.

18. The method of claim 17 further comprising using a single multi-mode synch controller to process the time and frequency error estimates produced by the multi-mode time filter and controlling the internal oscillator based on its input data.

19. The method of claim 17 further comprises deriving from a sequence of time error estimates said frequency error estimates obtained via external interfaces.

20. The method of claim 18 further comprises supplying to said multi-mode synch controller temperature estimates for use in frequency compensation of the internal oscillator.

41. The method of claim 17 further comprising estimating by the multi-mode time filter the bias in the externally derived time and frequency estimates and eliminating these biases during holdover.

21. A GPS clock module apparatus for providing syntonisation, synchronization, position or some combination to a wireless base station, micro-cell, pico-cell, femto-cell or access point, said module comprising an apparatus for providing holdover backup via at least one interface between the GPS clock module and external time or frequency references.

22. The apparatus of claim 21 in which one of the said at least one interfaces is a serial interface via which the GPS clock module is informed of errors in its time or frequency based on measurements made externally.

23. The apparatus of claim 21 in which one of the said at least one interfaces is an input via which the GPS clock module estimates the precise time or precise period associated with edges of an externally generated timing or frequency reference while fixing and then uses the estimated times of the edges or the periods between them to maintain its own estimates of time and frequency during holdover.

24. The apparatus of claim 23 in which the said externally generated frequency reference is derived by dividing a reference frequency from a reference oscillator.

25. The apparatus of claim 23 in which the said externally generated frequency reference is derived from an SDH link.

26. The apparatus of claim 23 in which the said externally generated timing reference is generated by an external GPS receiver.

27. The apparatus of claim 23 in which the said externally generated timing reference is derived from an SDH link.

28. The apparatus of claim 24 comprising a temperature sensor interfaced to the GPS clock module that enables the GPS clock module to characterize the temperature characteristics of the oscillator and to compensate for those characteristics during holdover.

29. The apparatus of claim 24 comprising another interface to the GPS clock module as an output used to control or discipline the said external reference oscillator so as to set its frequency error as closely as possible to zero.

30. The apparatus of claim 23 comprising one or more additional interfaces to the GPS clock module used to switch between external timing or frequency references.

31. The apparatus of claim 21 in which a separate synch controller firmware routine is used to process the externally derived frequency and/or time synchronization error estimates and oscillator control is switched from the GPS synch controller to the external synch controller during holdover.

32. The apparatus of claim 31 in which said frequency error estimates are derived from a sequence of time error estimates.

33. The apparatus of claim 31 in which the external synch controller is supplied with temperature estimates for use in frequency compensation of the internal oscillator.

34. The apparatus of claim 21 comprising a single multi-mode synch controller firmware routine processes frequency and time error estimates from a GPS time filter and frequency and/or time synchronization error estimates obtained via external interfaces and controls the internal oscillator based on a combination of all the error estimates available to it.

35. The apparatus of claim 34 in which said frequency error estimates obtained via external interfaces are derived from a sequence of time error estimates.

36. The apparatus of claim 34 in which the said multi-mode synch controller is supplied with temperature estimates for use in frequency compensation of the internal oscillator.

37. The apparatus of claim 21 in which a single multi-mode time filter processes GPS measurements and frequency and/or time synchronization error estimates obtained via external interfaces to estimate its time and frequency error based on a combination of all the measurements and error estimates available to it.

38. The apparatus of claim 37 in which a single multi-mode synch controller processes the time and frequency error estimates produced by the multi-mode time filter and controls the internal oscillator based on its input data.

39. The apparatus of claim 37 in which said frequency error estimates obtained via external interfaces are derived from a sequence of time error estimates.

40. The apparatus of claim 38 in which the said multi-mode synch controller is supplied with temperature estimates for use in frequency compensation of the internal oscillator.

42. The apparatus of claim 37 in which the multi-mode time filter estimates the bias in the externally derived time and frequency estimates and eliminates these biases during holdover.