SINGLE POLE MULTI THROW SWITCH

• US 20110105055A1
• Filed: 10/30/2009
• Published: 05/05/2011
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: ILKOV, Nikolay
• Granted Patent: US 8,306,481 B2
• Time in Patent Office: Days
• US Class Current: 455/93
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A single pole multi throw switch comprises a first switching unit, a second switching unit coupled to a common port and comprising a parasitic off state capacitance, and a matching unit. The matching unit may be coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive.

Claims

1. A single pole multi throw switch, comprising:

a first switching unit;

a second switching unit coupled to a common port and comprising a parasitic off state capacitance; and

a matching unit coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive.

2. The single pole multi throw switch according to claim 1, wherein the matching unit is configured to contribute to an impedance match if the first switching unit is inactive and the second switching unit is active.

3. The single pole multi throw switch according to claim 1, wherein the first switching unit comprises a parasitic off state capacitance, wherein the matching unit is configured, so that a contribution of the parasitic off state capacitance of the first switching unit to the impedance match, if the second switching unit is active, is lower than a contribution of the parasitic off state capacitance of the second switching unit to the impedance match, if the first switching unit is active.

4. The single pole multi throw switch according to claim 1, wherein the matching unit comprises a series inductor coupled between the first switching unit and the common port or comprises a parallel inductor comprising a first terminal coupled to a node between the first switching unit and the common port and comprising a second terminal coupled to a reference potential feed.

5. The single pole multi throw switch according to claim 1, wherein the matching unit comprises a series inductor coupled between the first switching unit and the common port and comprises a parallel inductor comprising a first terminal coupled to a node between the first switching unit and the series inductor and comprising a second terminal coupled to a reference potential feed.

6. The single pole multi throw switch according to claim 1, wherein the second switching unit is coupled to the common port through a direct connection.

7. The single pole multi throw switch according to claim 1, wherein an electrical connection between the second switching unit and the common port comprises an inductance lower than 10% of an inductance of an electrical path from the first switching unit through the matching unit to the common port.

8. The single pole multi throw switch according to claim 1, wherein the single pole multi throw switch is configured to switch at least one lower frequency signal and at least one higher frequency signal, wherein the matching unit is configured such that the impedance match caused by the matching unit is better for the higher frequency signal if switched by the first switching unit than an impedance match caused by the matching unit for the higher frequency signal if switched by the second switching unit.

9. The single pole multi throw switch according to claim 8, wherein the matching unit is configured such that the impedance match caused by the matching unit is better for the lower frequency signal if switched by the second switching unit than an impedance match caused by the matching unit for the lower frequency signal if switched by the first switching unit.

10. The single pole multi throw switch according to claim 1, wherein the first switching unit and the second switching unit comprise a switching device each, wherein each of the switching devices comprises a first terminal coupled to the matching unit, a second terminal configured to perform at least one of the following:

receive a signal to be provided to the common port, or provide a signal received from the common port and a control input,

wherein each of the switching devices is configured to be activated by a control signal received at the control input.

11. The single pole multi throw switch according to claim 10, wherein each of the switching devices comprises a plurality of series transistors, wherein the gates of the series transistors are coupled to the control input of the respective switching device, wherein a first transistor of the plurality of series transistors is coupled to the first terminal of the switching device, and wherein a last transistor of the plurality of series transistors is coupled to the second terminal of the respective switching device.

12. The single pole multi throw switch according to claim 10, wherein each of the switching device comprises a relay, a micromechanical switch, or a transistor.

13. A single pole multi throw switch, comprising:

a first switching unit;

a second switching unit coupled to a common port and comprising a parasitic off state capacitance; and

a matching unit coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive,

wherein the first switching unit comprises a first switching device and a second switching device, wherein the second switching unit comprises a first switching device and a second switching device,

wherein the matching unit comprises a series inductor and a parallel inductor, wherein the series inductor of the matching unit is coupled between the first switching unit and a common port and the parallel inductor comprises a first terminal coupled to a reference potential feed and a second terminal coupled to a node between the first switching unit and the series inductor,

wherein the first switching device of the first switching unit comprises a first terminal coupled to the series inductor and the parallel inductor of the matching unit and a second terminal coupled to a first port of the first switching unit, wherein the first switching device of the first switching unit comprises a control input configured to receive a control signal,

wherein the second device of the first switching unit comprises a first terminal coupled to a node between the matching unit and the first switching device of the first switching unit and a second terminal coupled to a second port of the first switching unit, wherein the second switching device of the first switching unit comprises a control input configured to receive a control signal,

wherein the first switching device of the second switching unit comprises a first terminal directly coupled to the common port and a second terminal coupled to a first port of the second switching unit, wherein the first switching device of the second switching unit comprises a control input configured to receive a control signal, and

wherein the second switching device of the second switching unit comprises a first terminal directly coupled to the common port and a second terminal coupled to a second port of the second switching unit, wherein the second switching device of the second switching unit comprises a control input configured to receive a control signal.

14. A single pole multi throw switch, comprising:

a first switching unit;

a second switching unit coupled to a common port and comprising a parasitic off state capacitance; and

a matching unit coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match as a pi-matching network between the first switching unit and the common port if the first switching unit is active and the second switching unit is inactive,

wherein the matching unit is configured to contribute to an impedance match as a shunt matching network between the common port and a reference potential feed if the first switching unit is inactive and the second switching unit is active, and

wherein the single pole multi throw switch is configured to switch at least one low frequency signal and at least one high frequency signal, wherein the matching unit is configured such that the impedance match caused by the matching unit is better for the high frequency signal if switched by the first switching unit than an impedance match caused by the matching unit for the high frequency signal if switched by the second switching unit.

15. A multi band transmitter, comprising:

a plurality of transmit units; and

a single pole multi throw switch, comprising;

a first switching unit,

a second switching unit coupled to a common port and comprising a parasitic off state capacitance, and

a matching unit coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive,

wherein each transmit unit of the plurality of transmit units that is coupled to the first switching unit is configured to provide a signal with a higher frequency than all frequencies of signals provided by all transmit units of the plurality of transmit units coupled to the second switching unit.

16. A multi band receiver, comprising:

a plurality of receive units; and

a single pole multi throw switch, comprising;

a first switching unit,

a second switching unit coupled to a common port and comprising a parasitic off state capacitance, and

a matching unit coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive,

wherein each receive unit of the plurality of receive units that is coupled to the first switching unit is configured to receive a signal with a higher frequency than all frequencies of signals received by all receive units of the plurality of receive units coupled to the second switching unit.

17. A method for using a single pole multi throw switch, wherein the single pole multi throw switch comprises a first switching unit, a second switching unit and a matching unit, wherein the second switching unit is coupled to a common port and comprises a parasitic off state capacitance, and wherein the matching unit is coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive, the method comprising:

activating the first switching unit to receive or provide a signal with a first frequency at the common port; and

activating the second switching unit to receive or provide a signal with a second frequency at the common port, wherein the first frequency is higher than the second frequency.

18. A single pole multi throw switch, comprising:

first switching means;

second switching means coupled to a common port and comprising a parasitic off state capacitance; and

matching means coupled between the first switching unit and the common port, for contributing, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive.