MICROCONTROLLER, CONTROL SYSTEM AND DESIGN METHOD OF MICROCONTROLLER

• US 20110106335A1
• Filed: 01/11/2011
• Published: 05/05/2011
• Est. Priority Date: 03/27/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sakata, Teruaki, Yamada, Hiromichi, Kanekawa, Nobuyasu
• Granted Patent: US 8,046,137 B2
• Time in Patent Office: Days
• US Class Current: 701/1
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1679 at clock signal level

Abstract

Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

Claims

1. A microcontroller comprising:

a first data processing unit operated in synchronization with a first clock signal;

a circuit unit operated in synchronization with the first clock signal based on a control of the first data processing unit;

a second data processing unit performing the same data processing as the first data processing unit with a delay from the first data processing unit for an identical process in synchronization with a second clock signal having the same cycle as the first clock signal;

a first interface circuit having a plurality of flip flops for holding a first signal outputted from the first data processing unit to the circuit unit;

a comparator which compares a second signal outputted from the second data processing unit in response to an output of the first signal by the first data processing unit and the signal held in the first interface circuit in synchronization with the second clock signal; and

a second interface circuit having a plurality of flip flops for holding a third signal supplied from the circuit unit to the first data processing unit and outputting the same to the second data processing unit,

wherein the plurality of flip flops in the first and second interface circuits include those using the first clock signal for defining a latch timing and those using the second clock signal for the same.

2. The microcontroller according to claim 1,

wherein the plurality of flip flops in the first and second interface circuits further include those using a third clock signal, which has the same cycle as the first clock signal, for defining the latch timing.

3. The microcontroller according to claim 2,

wherein the first signal is a command, an address and write data outputted from the first data processing unit to a bus,

wherein the second signal is a command, an address and write data outputted from the second data processing unit, and

wherein the third signal is read data and a command outputted from a memory to the bus in accordance with the command and the address outputted from the first data processing unit to the bus.

4. The microcontroller according to claim 3,

wherein the third signal is data outputted to the first data processing unit and the second data processing unit from a peripheral circuit operated in accordance with control data outputted from the first data processing unit.

9. A design method of a microcontroller for generating gate-level netlist from hardware description language of the microcontroller according to claim 1 by using a computer device, the design method comprising the steps of:

generating the gate-level netlist by inputting clock candidate data for specifying which of the first clock signal and the second clock signal is to be used as the latch clock of the respective flip flops, to computer devices together with hardware description language data; and

determining adequacy of a clock candidate by a timing check using the generated gate-level netlist.

10. The design method according to claim 9,

wherein the gate-level netlist is corrected so that an inadequate clock candidate is replaced with an adequate clock candidate based on a determination result about the adequacy of the clock candidate.

11. A design method of a microcontroller for generating gate-level netlist from hardware description language of the microcontroller according to claim 2 by using a computer device, the design method comprising the steps of:

generating the gate-level netlist by inputting clock candidate data for specifying which of the first clock signal, the second clock signal and the third clock signal is to be used for specifying latch timings of the respective flip flops, to computer devices together with hardware description language data; and

determining adequacy of a clock candidate by a timing check using the generated gate-level netlist.

12. The design method according to claim 11,

wherein the gate-level netlist is corrected so that an inadequate clock candidate is replaced with an adequate clock candidate based on a determination result about the adequacy of the clock candidate.

5. A control system for controlling an automotive powertrain system, the control system comprising:

a control circuit;

a sensor having an output connected to the control circuit; and

an actuator whose operation is controlled by the control circuit,

wherein the control circuit includes;

a first data processing unit operated in synchronization with a first clock signal;

a circuit unit operated in synchronization with the first clock signal based on a control of the first data processing unit;

a second data processing unit performing the same data processing as the first data processing unit with a delay from the first data processing unit for an identical process in synchronization with a second clock signal having the same cycle as the first clock signal;

a first interface circuit having a plurality of flip flops for holding a first signal outputted from the first data processing unit to the circuit unit;

a comparator which compares a second signal outputted from the second data processing unit in response to an output of the first signal by the first data processing unit and the signal held in the first interface circuit in synchronization with the second clock signal; and

a second interface circuit having a plurality of flip flops for holding a third signal supplied from the circuit unit to the first data processing unit and outputting the same to the second data processing unit, and

wherein the plurality of flip flops in the first and second interface circuits include those using the first clock signal for defining a latch timing and those using the second clock signal for the same.

6. The control system according to claim 5,

wherein the plurality of flip flops in the first and second interface circuits further include those using a third clock signal, which has the same cycle as the first clock signal, for defining the latch timing.

7. The microcontroller according to claim 6,

wherein the first signal is a command, an address and write data outputted from the first data processing unit to a bus,

wherein the second signal is a command, an address and write data outputted from the second data processing unit, and

wherein the third signal is read data and a command outputted from a memory to the bus in accordance with the command and the address outputted from the first data processing unit to the bus.

8. The microcontroller according to claim 7,

wherein the third signal is data outputted to the first data processing unit and the second data processing unit from a peripheral circuit operated in accordance with control data outputted from the first data processing unit.