SYSTEM FOR ADDRESS-EVENT-REPRESENTATION NETWORK SIMULATION
First Claim
1. A system for address-event-representation network simulation comprising:
- a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes, wherein each node comprises;
a source table configured to receive an input message and identify a weight associated with a source of the input message;
state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state; and
a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message.
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Accused Products
Abstract
A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
58 Citations
24 Claims
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1. A system for address-event-representation network simulation comprising:
a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes, wherein each node comprises; a source table configured to receive an input message and identify a weight associated with a source of the input message; state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state; and a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for address-event-representation network simulation, comprising:
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receiving an input message at a source table of a node in a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes; identifying a weight associated with a source of the input message, the identified weight located in the source table; updating a node state as a function of the identified weight, the updating performed by state management logic; generating an output signal responsive to the updated node state; accessing a target table to identify a target to receive an output message; and generating the output message in response to the output signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes, wherein each node comprises; a source table configured to receive an input message and identify a weight associated with a source of the input message; state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state; and a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. - View Dependent Claims (22, 23, 24)
Specification