Neuromorphic computer

• US 20110106742A1
• Filed: 11/05/2009
• Published: 05/05/2011
• Est. Priority Date: 11/05/2009
• Status: Active Grant

• Current Assignee: United States Air Force
• Original Assignee: United States Air Force
• Inventors: Pino, Robinson E.
• Granted Patent: US 8,275,728 B2
• Time in Patent Office: Days
• US Class Current: 706/33
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods.

Claims

1. A neuromorphic computing device, comprising:

at least one input;

at least one output;

a plurality of synapse circuits electrically interconnecting said at least one input to said at least one output;

said plurality of synapse circuits being configured in successive layers, each successive layer having at least one synapse circuit;

wherein a subsequent said successive layer possesses fewer said synapse circuits than an immediately prior said successive layer; and

a plurality of floating voltage adding nodes;

wherein each of said plurality of floating voltage adding nodes electrically connects and sums outputs corresponding to at least two of said plurality of synapse circuits of any one said successive layer.

2. The neuromorphic computing device of claim 1, wherein said synapse circuit further comprises

an input;

an output;

a variable resistance element having an input and an output; and

an output circuit having an input and an output;

wherein

said input of said synapse circuit is electrically connected to said input of said variable resistance element;

said output of said variable resistance element is electrically connected to said input of said output circuit;

said output of said output circuit is electrically connected to said output of said synapse circuit; and

wherein said variable resistance element controls the connection strength between said synapse circuits and said floating voltage adding nodes.

3. The neuromorphic computing device of claim 2, wherein said variable resistance element further comprises a transistor biased in its linear operating region.

4. The neuromorphic computing device of claim 2, wherein said variable resistance element further comprises a memristor.

5. The neuromorphic computing device of claim 2, wherein said output circuit is an inverter circuit, said inverter circuit being responsive to an input so as to produce a minimum and a maximum output voltage.

6. The neuromorphic computing device of claim 5, wherein said inverter circuit comprises

a p-field effect transistor having a gate, a drain, and a source;

and

a n-field effect transistor having a gate, a drain and a source;

wherein

said gate of said p-field effect transistor is electrically connected to said gate of said n-field effect transistor and to said input of said inverter circuit; and

said source of said p-field effect transistor is electrically connected to said drain of said n-field effect transistor and to said output of said inverter circuit.

7. The neuromorphic computing device of claim 1, wherein said subsequent said successive layer possesses half as many said synapse circuits than an immediately prior said successive layer.

8. The neuromorphic computing device of claim 6 having said variable resistance element comprising said transistor biased in its linear operating region, wherein said output of said synapse circuit outputs a signal SO(SI, Vm) according to the relationship