Method, Apparatus and Instructions for Parallel Data Conversions

• US 20110106867A1
• Filed: 01/07/2011
• Published: 05/05/2011
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Gopalan Ramanujam
• Original Assignee: Gopalan Ramanujam
• Inventors: Ramanujam, Gopalan
• Granted Patent: US 8,533,244 B2
• Time in Patent Office: Days
• US Class Current: 708/204
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Claims

1-33. -33. (canceled)

34. A processor comprising:

a destination storage location corresponding to a first register;

an execution unit having circuitry to process a packed format values by converting a first packed first format value in a first format to a first plurality of second format values, the first packed first format value having at least three sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, the execution unit to store all of the first plurality of second format values into the first register.

35. The processor of claim 34, wherein the first packed first format value represents a part of a pixel data.

36. The processor of claim 34, wherein the first packed first format value is from a first plurality of packed first format values.

37. The processor of claim 34, wherein the first register is a 64-bit register, wherein the first number of bits is 5 bits and the second number of bits is 8 bits.

38. The processor of claim 34, wherein the first packed first format value is stored in a lower half portion of a source location.

39. The processor of claim 34, wherein the first packed first format value is stored in a higher half portion of a source location.

40. The processor of claim 34, further comprising a floating-point unit, wherein the processor is capable of performing out-of-order execution.

41. The processor of claim 34, further comprising buffers, memory, cache, and arithmetic logic unit (ALU).

42. A system comprising:

a processor including;

a destination storage location corresponding to a first register; and

an execution unit having circuitry to process a packed format values by converting a first packed first format value in a first format to a first plurality of second format values, the first packed first format value having at least three sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, the execution unit to store all of the first plurality of second format values into the first register;

a graphics interface coupled to the processor; and

a display coupled to the graphics interface.

43. The system of claim 42, wherein the first packed first format value represents a part of a pixel data.

44. The system of claim 42, wherein the first packed first format value is from a first plurality of packed first format values.

45. The system of claim 42, wherein the first register is a 64-bit register, wherein the first number of bits is 5 bits and the second number of bits is 8 bits.

46. The system of claim 42, wherein the first packed first format value is stored in a lower half portion of a source location.

47. The system of claim 42, wherein the first packed first format value is stored in a higher half portion of a source location.

48. The system of claim 42, further comprising a floating-point unit, wherein the processor is capable of performing out-of-order execution.

49. The system of claim 42, further comprising buffers, memory, cache, and arithmetic logic unit (ALU).