COMMUNICATIONS CONTROL BUS AND APPARATUS FOR CONTROLLING MULTIPLE ELECTRONIC HARDWARE DEVICES

• US 20110106996A1
• Filed: 04/25/2008
• Published: 05/05/2011
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: Roberto Rosso
• Original Assignee: Roberto Rosso
• Inventors: Rosso, Roberto
• Granted Patent: US 8,583,843 B2
• Time in Patent Office: Days
• US Class Current: 710/300
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

Disclosed is a communications control bus. The bus comprises an IMB slave CPU, at least two registers, and a three bit data connector, which connects the two registers. The connector permits transmission of a three bit data signal between the two registers. A network interconnects the two registers and the IMB slave CPU.

Claims

1. A communications control bus, the bus comprising:

a) an IMB slave CPU;

b) at least two registers;

c) a first three bit data connector for connecting the at least two registers, the connector permitting transmission of a three bit data signal between the at least two registers; and

d) a network interconnecting the at least two registers and the IMB slave CPU.

2. The bus, according to claim 1, in which the at least two registers comprise:

a) a first control register; and

b) a first data register;

e) the network interconnecting the first control register and the first data register, the network being configured such that in response to a first at least 8 bit data signal being received at the first control register, a first 3 bit disable command signal is transmitted by the first control register to the first data register.

3. The bus, according to claim 2, the at least two registers further comprise:

a) a second control register;

b) a second data register;

c) a third control register;

d) a third data register;

e) a fourth control register; and

f) a fourth data register;

g) the network being configured such in response to second, third, and fourth at least 8 bit data signals being received respectively at the second, third and fourth control registers, a second, third and fourth 3 bit disable command signal is transmitted to the respective second, third and fourth data registers.

4. The bus, according to claims 2 or 3, in which the network is configured such in response to fifth, sixth, seventh and eighth at least 8 bit data signals being received respectively at the first, second, third and fourth control registers, a fifth, sixth, seventh, and eighth 3 bit load command signal is transmitted to the respective first, second, third and fourth data registers so that each data register is permitted to receive at least 8 bits of data.

5. The bus, according to claim 4, in which the network is configured such in response to ninth, tenth, eleventh and twelfth at least 8 bit data signals being received respectively at the first, second, third and fourth control registers, a fifth, sixth, seventh and eighth 3 bit disable command signal is transmitted to the respective first, second, third and fourth data registers.

6. The bus, according to claim 5, in which the network is configured such in response to a 3 bit unload command signal is transmitted to the respective first, second, third and fourth data registers from the respective first, second, third and fourth control registers, the at least 8 bits of data stored in the data registers is transmitted to the IMB slave CPU.

7. The bus, according to claims 2 or 3, in which the first control register is paired with the first data register;

the second control register is paired with the second data register;

the third control register is paired with the third data register; and

the fourth control register is paired with the fourth data register.

8. The bus, according to claim 1, in which the at least two registers are connected by a 3 bit command signal.

9. The bus, according to claim 3, in which a first 32 bit stream of data is received by the first, second, third and fourth control registers.

10. The bus, according to claim 3, in which a second 32 bit stream of data is received by the first, second, third and fourth data registers.

11. The bus, according to claim 10, in which the second 32 bit stream of data is transmitted from the fourth data register to the IMB slave CPU.

12. The bus, according to claim 2, in which an SL1 signal wire connects the IMB slave CPU to the first control register.

13. The bus, according to claim 2, in which an SL2 signal wire connects the IMB slave CPU to the first data register.

14. The bus, according to claim 3, in which a first clock signal wire interconnects the first, second, third and fourth control registers to the IMB slave CPU.

15. The bus, according to claim 3, in which an enable signal wire interconnects the first, second, third and fourth control registers to the IMB slave CPU.

16. The bus, according to claim 3, in which a second clock signal wire connects the first, second, third and fourth data registers to the IMB slave CPU.

17. The bus, according to claim 3, in which a DQA feedback wire connects the fourth data register to the IMB slave CPU.

18. The bus, according to claim 3, in which each control register includes at least one input/output pin and each data register includes at least one input/output pin.

19. The bus, according to claim 7, in which at least three wires interconnect each paired control register and data register.

20. The bus, according to claim 19, in which each control register transmits a 3 bit command signal to each data register located adjacent thereto.

21. The bus, according to claim 1, in which the at least two registers and the first three bit data connector comprise a 13 bit bus.

22. The bus, according to claim 21, in which the 13 bit bus includes an eight bit bi-directional data register and five most significant output bits of an adjacent control register.

23. The bus, according to claim 22, in which the first three bit data connector issues a command to the adjacent control register.

24. The bus, according to claim 7, in which at least one ACM connector is connected to each pair of control registers and data registers.

25. The bus, according to claim 24, includes four ACM connectors.

26. The bus, according to claim 24, further comprising a HUS and a MUC.

27. The bus, according to claim 26, in which each IMB includes at least four MUCs.

28. A modular apparatus for controlling multiple electronic hardware devices, the apparatus comprising:

a) at least one intelligent master base for use with an electrical circuit;

b) a first communications control bus, according to claim 1, located in the intelligent master base; and

c) at least one adaptable cube module connected to the intelligent master base, the communications control bus being adapted to allow the number of adaptable cube modules to be increased in multiples of four.

29. The apparatus, according to claim 28, in which an intelligent slave base is connected to the intelligent master base.

30. The apparatus, according to claim 29, in which a second communications control bus is located in the intelligent slave base.

31. The apparatus, according to claim 28, in which the intelligent master base and the adaptable cube module are sized and shaped for location in an electrical box.

32. The apparatus, according to claim 28, in which a smart plate is connected to the adaptable cube module.

33. The apparatus, according to claim 29, in which a smart plate is connected to the intelligent slave base.

34. The apparatus, according to claim 28, in which a smart plate is connected to the intelligent master base.

35. The apparatus, according to claim 28, in which a slim slave base module is connected to the intelligent master base.

36. The apparatus, according to claim 28, in which a slim slave base module is connected to the intelligent slave base.

37. The apparatus, according to claim 28, in which the intelligent master base comprises:

a) an IMB master CPU;

b) an IMB slave CPU electrically connected to the IMB master CPU via an I²C standard;

c) at least two adaptable cube module connectors for receiving the adaptable cube modules;

d) a first HUS bus interconnecting the at least two adaptable cube module connectors to the IMB slave CPU;

e) a circuit for remotely controlling the multiple electronic hardware devices, the circuit being connected to the IMB slave CPU; and

f) a power supply for powering the circuit, the IMB master CPU, and the IMB slave CPU, the power supply being connected to an electrical wiring network.

38. The apparatus, according to claim 37, in which the IMB slave CPU is a PIC micro-controller or DSC/DSP processors.

39. The apparatus, according to claim 28, in which each adaptable cube module connector is at least a 28 pin header.

40. The apparatus, according to claim 37, further includes an RF transceiver chip having a mesh topology stack, the stack communicating information in the format of the SPTN communications protocol.

41. The apparatus, according to claim 29, in which the intelligent slave base further comprises:

a) an ISB master CPU;

b) at least two adaptable cube module connectors for receiving the adaptable cube modules;

c) a second communications control bus located in the intelligent slave base; and

d) a second HUS bus interconnecting the at least two adaptable cube module connectors to the ISB master CPU; and

e) a power supply for powering the ISB master CPU, the power supply being connected to the IMB.

42. The apparatus, according to claim 28, in which each adaptable cube module comprises:

a) an adaptable cube module connector for receiving the intelligent master base;

b) a conductive circuit having an eight bit bus portion, and first and second routes;

c) an 8 bit bus control buffer connected to the second route; and

d) a plurality of resistors connected to the first route, the resistors defining an address of the adaptable cube module, the conductive circuit communicating data from the intelligent master base to the resistors.

43. The apparatus, according to claim 42, includes the adaptable cube module connector includes a plurality of connections for use with HUS services.

44. The apparatus, according to claim 42, in which the conductive circuit further comprises a buffer latch control connected to an output of a control register.

45. The apparatus, according to claim 42, further comprises a smart plate cover interface.

46. The apparatus, according to claim 45, in which the smart plate cover interface and the adaptable cube module are one-piece.

47. The apparatus, according to claim 42, in which the resistors are parallel pull up or pull down resistors.

48. The apparatus, according to claim 29, wherein the intelligent slave base and the intelligent master base are connected by a base expansion connector.

49. The apparatus, according to claim 48, in which the base expansion connector comprises an I²C standard.

50. The apparatus, according to claim 45, in which the smart plate includes a smoke detector, at least one infra red proximity detector, at least one motion detector, at least one GFI (Ground fault interruption), at least one Arc detection, or at least one lighting dimmer circuit.

51. The apparatus, according to claim 31, in which the intelligent master base and the adaptable cube module are located in an 1104, 4×

4 or 4/11/16, 6×

6, 8×

8, 10×

10, 12×

12, 16×

16 or 24×

24 electrical box.

52. The apparatus, according to claim 35, in which the slim slave base module comprises a PC board for communicating conductive traces between base expansion connectors, the board having located therein a plurality of holes through which power conductors pass independent of the conductive traces.

53. The apparatus, according to claim 35, in which the slim slave base module comprises a PC board for communicating conductive traces between base expansion connectors, the board having a plurality of housing terminal screws for connecting to the electrical wiring system.

58. (withdrawn;

currently amended) An intelligent slave base comprising;

a) an ISB master CPU;

b) four cube module connectors for receiving respectively four adaptable cube modules;

c) a communications control bus according to claim 1;

d) a HUS bus interconnecting the adaptable cube module connectors to the ISB master CPU; and

e) a power supply for powering the ISB master CPU, the power supply being connectable to an intelligent master base.

65. The apparatus, according to claim 32, in which the smart plate includes features selected from the group consisting of:

a graphical color touch screen, a battery charger, proximity sensors, a long range motion sensor, a thermostat, a lux meter (TAOS technology, a smoke detector, doorbell buzzer system, video camera images, a humidistat an intercom system an intrusion system, a camera, programmable control function blocks, a permanent or/and detachable nightlight, virtual switches/dimmers, telephone and smart tagging systems, displays readings associated to the establishment'"'"'s hot water tank(s) which determine the amount of hot water available per tank.

66. The apparatus, according to claim 31, in which the electrical box includes any a combination of one or more hardware devices selected from the group consisting of:

IMB, ISB, MUCX'"'"'s, RF communications in the IMB, lighting dimmer circuits, connectivity for a graphical color touch screen, a long range motion detector, thermostat, a lux meter (TAOS technology), smoke detector, doorbell buzzer button, humidistat, intercom, camera, battery charger, GFI (Ground fault interruption), arc detector, single or duplex receptacles, motion sensor, single/double pole button switches, AC/DC discrete low/high voltage input, AC/DC discrete low/high voltage output, DC analog voltage/current output, DC analog voltage/current input, CO₂ sensor, RS232 RF links, DAC, ADC, on/off photocell, RS232, RF-RS-232, RS-422, RS-485, RF-RS-422, RF-RS-485, pulse width modulator output, buzzer, night light, power bar with electrical cord, witch/dimmer buttons and battery charger.

67. The apparatus, according to claim 37, in which the intelligent master base is cuboid.

68. The apparatus, according to claim 41, in which the intelligent slave base is cuboid.

69. The apparatus, according to claim 42, in which the adaptable cube module is cuboid.

72. A circuit for remotely controlling multiple hardware devices, the circuit comprising a communications control bus, according to claim 1.

79. A method of controlling multiple electronic hardware devices using a touchless smart plate interface having a proximity detector, the smart plate interface being connected to a modular apparatus, according to claim 28, the method comprising:

waving a hand at least once near the proximity detector to control operation of a first electronic hardware device.

80. The method, according to claim 79 further comprising, after waving the hand at least once, pausing the hand near the proximity detector so as to further control operation of the first electronic hardware device.

81. The method, according to claim 79, in which two consecutive hand wavings near the proximity detector operates a second electronic hardware device.

82. The method, according to claim 81, in which two consecutive having wavings followed by a pause near the proximity detector further controls operation of the second hardware device.

83. The method, according to claim 79, in which three consecutive hand wavings near the proximity detector operates a third electronic hardware device.

84. The method, according to claim 83, in which three consecutive hand wavings followed by a pause near the proximity detector further controls the third electronic hardware device.

85. The method, according to claim 79, in which the hand is moved orthogonal to the proximity detector so as to further control the electronic device.

86. The method, according to claim 85, in which the hand is moved orthogonal to the proximity detector so as to dim lights.

54. An intelligent master base comprising:

a) an IMB master CPU;

b) an IMB slave CPU electrically connected to the IMB master CPU via an I²C standard;

c) four adaptable cube module connectors for receiving respectively four adaptable cube modules;

d) a HUS bus interconnecting the adaptable cube module connectors to the IMB slave CPU;

e) a circuit for remotely the controlling the multiple electronic hardware devices, the circuit being connected to the IMB slave CPU; and

f) a power supply for powering the circuit, the IMB master CPU, and the IMB slave CPU, the power supply being connected to an electrical wiring network.

55. The intelligent master base, according to claim 54, in which the IMB slave CPU is a PIC micro-controller or DSC/DSP processors.

56. The intelligent master base, according to claim 54, in which each adaptable cube module connector is at least a 28 pin header.

57. The intelligent master base, according to claim 54, further includes an RF transceiver chip having a mesh topology stack, the stack communicating information in the format of the SPTN communications protocol.

59. An adaptable cube module comprising:

a) an adaptable cube module connector for receiving an intelligent master base;

b) a conductive circuit having an eight bit bus portion, and first and second routes;

c) an 8 bit bus control buffer connected to the second route; and

d) a plurality of resistors connected to the first route, the resistors defining an address of the adaptable cube module, the conductive circuit communicating data from the intelligent master base to the resistors.

60. The adaptable cube module, according to claim 59, in which the adaptable cube module connector includes a plurality of connections for use with HUS services.

61. The adaptable cube module, according to claim 59, in which the conductive circuit further comprises a buffer latch control connected to an output of a control register.

62. The adaptable cube module, according to claim 59, in which the resistors are parallel pull up or pull down resistors.

63. A slim slave base module comprising:

a PC board for communicating conductive traces between base expansion connectors, the board having located therein a plurality of holes through which power conductors pass independent of the conductive traces.

64. A slim slave base module comprising a PC board for communicating conductive traces between base expansion connectors, the board having a plurality of housing terminal screws for connecting to the electrical wiring system.

70. A one-piece apparatus for controlling multiple electronic hardware devices, the apparatus comprising:

a) an adaptable cube module connectable to an intelligent master base; and

b) a smart plate cover interface connected to the adaptable cube module.

71. The apparatus, according to claim 70, in which the smart plate includes features selected from the group consisting of:

a graphical color touch screen, a battery charger, proximity sensors, a long range motion sensor, a thermostat, a lux meter (TAOS technology, a smoke detector, doorbell buzzer system, video camera images, a humidistat an intercom system an intrusion system, a camera, programmable control function blocks, a permanent or/and detachable nightlight, virtual switches/dimmers, telephone and smart tagging systems, displays readings associated to the establishment'"'"'s hot water tank(s) which determine the amount of hot water available per tank.

73. A method of remotely controlling multiple electronic hardware devices using a communications control bus, the method comprising:

a) electrically interconnecting a first control register, a first data register, and an IMB slave CPU; and

b) transmitting a three bit data disable signal from the first control register to the first data register.

74. The method, according to claim 73, further comprising:

a) receiving a first at least 8 bit data signal at the first control register; and

b) transmitting a first 3 bit disable signal from the first control register to the first data register.

75. The method, according to claim 74, further comprising:

a) receiving second, third, and fourth at least 8 bit data signals at respective second, third and fourth control registers; and

b) transmitting a second, third and fourth 3 bit disable command signal to the respective second, third and fourth data registers.

76. The method, according to claim 75, further comprising:

a) receiving fifth, sixth, seventh and eighth at least 8 bit data signals respectively at the first, second, third and fourth control registers allowing its previous first, second, third and fourth data bytes to be transferred to the fifth, sixth, seventh and eighth control registers; and

b) transmitting a fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth 3 bit load command signal to the respective first, second, third, fourth, fifth, sixth, seventh and eighth data registers so that each data register is permitted to receive at least 8 bits of data.

77. The method, according to claim 76, further comprising:

a) receiving ninth, tenth, eleventh and twelfth at least 8 bit data signals respectively at the first, second, third and fourth control registers allowing its previous fifth, sixth, seventh and eighth data bytes to be transferred to the fifth, sixth, seventh and eighth control registers; and

b) transmitting a thirteenth, fourteenth, fifteenth sixteenth, seventeenth, eighteenth, nineteenth and twentieth, 3 bit disable command signal to the respective first, second, third fourth, fifth, sixth, seventh and eighth data registers.

78. The method, according to claim 77, further comprising:

a) transmitting a 3 bit unload command signal to the respective first, second, third, fourth, fifth, sixth, seventh and eighth data registers from the respective first, second, third, fourth, fifth, sixth, seventh and eighth control registers; and

b) transmitting the at least 8 bits of data stored in the data registers to the IMB slave CPU.