SAVING POWER WHEN IN OR TRANSITIONING TO A STATIC MODE OF A PROCESSOR

• US 20110107131A1
• Filed: 01/10/2011
• Published: 05/05/2011
• Est. Priority Date: 10/23/2000
• Status: Active Grant

• Current Assignee: HD Silicon Solutions LLC (f/k/a Innovative Silicon Solutions, LLC)
• Original Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Inventors: Halepete, Sameer, Klayman, Keith, Read, Andrew
• Granted Patent: US 9,436,264 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Claims

1. A method comprising:

transitioning a processor to a reduced operation mode; and

reducing a voltage to the processor to a level that is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode.

2. The method of claim 1, wherein said transitioning comprises:

disabling a clock of the processor.

3. The method of claim 1, wherein the level is sufficient to permit the processor to transition out of the reduced operation mode within a predetermined period.

4. The method of claim 1, wherein the reduced operation mode is a deep sleep mode.

5. The method of claim 1, wherein said transitioning comprises transitioning a voltage regulator from a first regulation mode to a second regulation mode, and wherein said reducing comprises generating the voltage by using the voltage regulator.

6. The method of claim 5, wherein the voltage regulator comprises a feedback circuit coupled to an output terminal of the voltage regulator.

7. The method of claim 1, wherein said transitioning comprises:

monitoring a stop clock signal.

8. An apparatus comprising:

a processor configured to operate in a reduced operation mode; and

a circuit configured to output a voltage to the processor, wherein the voltage is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode.

9. The apparatus of claim 8, wherein a clock of the processor is disabled in the reduced operation mode.

10. The apparatus of claim 8, wherein the voltage is sufficient to permit the processor to transition out of the reduced operation mode within a predetermined period.

11. The apparatus of claim 8, wherein the reduced operation mode is a deep sleep mode.

12. The apparatus of claim 8, wherein the circuit comprises a voltage regulator, and wherein the voltage regulator comprises a feedback circuit coupled to an output terminal of the voltage regulator.

13. The apparatus of claim 12, wherein the voltage regulator is configured to operate in a first regulation mode and in a second regulation mode.

14. The apparatus of claim 13, wherein the voltage regulator generates the voltage while operating in the second regulation mode.

15. The apparatus of claim 8, wherein the processor operates in the reduced operation mode in response to a stop clock signal.

16. A circuit comprising:

an input terminal;

an output terminal; and

a voltage regulator coupled to the input and output terminals, wherein the voltage regulator is configured to generate a voltage that is sufficient to retain a memory state of a processor while the processor operates in a reduced operation mode.

17. The circuit of claim 16, wherein the voltage is sufficient to permit the processor to transition out of the reduced operation mode within a predetermined period.

18. The circuit of claim 16, wherein the voltage regulator is configured to operate in a first regulation mode and in a second regulation mode.

19. The circuit of claim 18, wherein the voltage regulator generates the voltage while operating in the second regulation mode.

20. The circuit of claim 16, wherein the reduced operation mode is a deep sleep mode.

21. The circuit of claim 16, wherein the voltage regulator includes a feedback circuit coupled to the output terminal.