SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110108837A1
• Filed: 11/03/2010
• Published: 05/12/2011
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: MIYAKE, Hiroyuki, YAMAZAKI, Shunpei, KOYAMA, Jun
• Granted Patent: US 8,633,480 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Claims

1. A semiconductor device comprising:

a pixel portion including a first transistor over a substrate;

a driver circuit portion including a second transistor over the substrate,

wherein the first transistor comprises;

a first gate electrode layer over the substrate;

a first insulating layer over the first gate electrode layer;

a first oxide semiconductor layer over the first insulating layer, the first oxide semiconductor layer including a first crystalline region in a superficial portion of the first oxide semiconductor layer;

a first source electrode layer overlapping with part of the first oxide semiconductor layer;

a first drain electrode layer overlapping with part of the first oxide semiconductor layer; and

a second insulating layer over the first source electrode layer and the first drain electrode layer and in contact with part of the first oxide semiconductor layer, and

wherein the second transistor comprises;

a second oxide semiconductor layer over the first insulating layer, the second oxide semiconductor layer including a second crystalline region in a superficial portion of the second oxide semiconductor layer;

a second source electrode layer overlapping with part of the second oxide semiconductor layer;

a second drain electrode layer overlapping with part of the second oxide semiconductor layer;

the second insulating layer over the second source electrode layer and the second drain electrode layer and in contact with part of the second oxide semiconductor layer; and

a second gate electrode layer over the second oxide semiconductor layer with the second insulating layer interposed therebetween.

2. The semiconductor device according to claim 1,

wherein the first crystalline region includes nanocrystals, and

wherein the second crystalline region includes nanocrystals.

3. The semiconductor device according to claim 1,

wherein the first crystalline region includes nanocrystals whose c-axes are oriented in a direction perpendicular to a surface of the first oxide semiconductor layer, and

wherein the second crystalline region includes nanocrystals whose c-axes are oriented in a direction perpendicular to a surface of the second oxide semiconductor layer.

4. The semiconductor device according to claim 1, further comprising:

an oxide conductive layer between the second oxide semiconductor layer and the second source electrode layer; and

an oxide conductive layer between the second oxide semiconductor layer and the second drain electrode layer.

5. The semiconductor device according to claim 1, wherein the second transistor is provided in a shift register in the driver circuit portion.

6. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise same material.

7. A display device comprising the semiconductor device according to claim 1.

8. A light-emitting device comprising the semiconductor device according to claim 1 and a light-emitting element.

9. An electronic device, comprising the semiconductor device according to claim 1, wherein the electronic device is selected from the group consisting of a television device, a digital camera, a digital video camera, a digital photo frame, a mobile phone, and an electronic paper.

10. A manufacturing method of a semiconductor device comprising the steps of:

forming a first gate electrode layer over a substrate;

forming a first insulating layer over the first gate electrode layer;

forming a first oxide semiconductor layer and a second oxide semiconductor layer over the first insulating layer, wherein the first oxide semiconductor layer is formed so as to overlap with the first gate electrode layer with the first insulating layer interposed therebetween;

performing a first heat treatment on the first oxide semiconductor layer and the second oxide semiconductor layer, so that a first crystalline region is formed in a superficial portion of the first oxide semiconductor layer and a second crystalline region is formed in a superficial portion of the second oxide semiconductor layer;

forming a first source electrode layer and a first drain electrode layer over the first oxide semiconductor layer, and a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer;

forming a second insulating layer over the first source electrode layer, the first drain electrode layer, the second source electrode layer, and the second drain electrode layer so as to be in contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer and so as to cover the first source electrode layer, the second source electrode layer, the first drain electrode layer, and the second drain electrode layer; and

forming a second gate electrode layer over the second insulating layer so as to overlap with the second oxide semiconductor layer.

11. The manufacturing method of a semiconductor device according to claim 10, wherein the first heat treatment is performed using a rapid thermal annealing method.

12. The manufacturing method of a semiconductor device according to claim 10,

wherein the first crystalline region includes nanocrystals, and

wherein the second crystalline region includes nanocrystals.

13. The manufacturing method of a semiconductor device according to claim 10,

wherein the first crystalline region includes nanocrystals whose c-axes are oriented in a direction perpendicular to a surface of the first oxide semiconductor layer, and

wherein the second crystalline region includes nanocrystals whose c-axes are oriented in a direction perpendicular to a surface of the second oxide semiconductor layer.

14. The manufacturing method of a semiconductor device according to claim 10,

wherein the second source electrode layer is formed over the second oxide semiconductor layer with an oxide conductive layer interposed therebetween, and

wherein the second drain electrode layer is formed over the second oxide semiconductor layer with an oxide conductive layer interposed therebetween.

15. The manufacturing method of a semiconductor device according to claim 10, further comprising the step of:

performing a second heat treatment after forming the second insulating layer.