SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20110108888A1
• Filed: 11/18/2010
• Published: 05/12/2011
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: NuPGA Corporation
• Inventors: Beinglass, Israel, Cronquist, Brian, de Jong, J. L., Sekar, Deepak C., Or-Bach, Zvi
• Granted Patent: US 8,754,533 B2
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Claims

1. A semiconductor device comprising;

a first mono-crystallized layer comprising

first transistors, and

a first metal layer forming at least a portion of connections between said first transistors; and

a second layer comprising second transistors, said second transistors consisting essentially of mono-crystalline material, said second layer overlying said first metal layer,

wherein said first metal layer comprises aluminum or copper, and

wherein said second layer is less than one micron in thickness and comprises logic cells.

2. A semiconductor device according to claim 1, wherein at least one of said second transistors is a recessed channel array transistor.

3. A semiconductor device according to claim 1, wherein at least one of said second transistors is a junction-less transistor.

4. A semiconductor device according to claim 1, wherein at least one of said second transistors is formed by a gate replacement process.

5. A semiconductor device according to claim 1, wherein said second transistors are substantially horizontally oriented transistors.

6. A semiconductor device according to claim 1 wherein said device is part of a mobile system.

7. A semiconductor device according to claim 1 wherein at least one portion of said first transistors and at least one portion of said second transistors are processed by a common lithography step.

8. A semiconductor device according to claim 1 wherein at least a portion of said second transistors overlays a portion of said first transistors.

9. A semiconductor device according to claim 1,

wherein at least said first mono-crystallized layer or said first metal layer comprises a first alignment mark,

wherein said second layer comprises a second alignment mark and at least one connection path between said first transistors and said second transistors, and

wherein said path comprises a via aligned in a first direction to said first alignment mark and in a second direction to said second alignment mark.

10. A semiconductor device, comprising:

a first mono-crystallized layer, comprising

first transistors, and

a first metal layer forming at least a portion of connections between said first transistors, and

a second layer comprising second transistors, said second transistors consisting essentially of mono-crystalline material, said second layer overlying said first metal layer,

wherein said first metal layer comprises aluminum or copper, and

wherein said second layer is less than one micron in thickness and comprises memory bit cells forming at least one memory structure.

11. A semiconductor device according to claim 10 wherein at least one of said second transistors is a recessed channel array transistor.

12. A semiconductor device according to claim 10 wherein at least one of said second transistors is a junction-less transistor.

13. A semiconductor device according to claim 10 wherein at least one of said second transistors is formed by a gate replacement process.

14. A semiconductor device according to claim 10 wherein said second transistors are substantially horizontally oriented transistors.

15. A semiconductor device according to claim 10 wherein said device is part of a mobile system.

16. A semiconductor device according to claim 10 wherein at least one portion of said first transistors and at least one portion of said second transistors are processed by a common lithography step.

17. A semiconductor device according to claim 10 wherein at least a portion of said second transistors overlays at least a portion of said first transistors.

18. A semiconductor device according to claim 10,

wherein at least said first mono-crystallized layer or said first metal layer comprises a first alignment mark,

wherein said second layer comprises a second alignment mark and at least one connection path between said first transistors and said second transistors, and

wherein said path comprises a via aligned in a first direction to said first alignment mark and in a second direction to said second alignment mark.

19. A semiconductor device according to claim 10, further comprising:

a third layer comprising third transistors, said third transistors consisting essentially of mono-crystalline material,

wherein said third layer substantially overlays said first metal layer, and

wherein said memory bit cells comprise said third transistors.

20. A semiconductor device comprising:

a first mono-crystallized layer comprising;

first transistors, and

a first metal layer forming at least a portion of connections between said first transistors, and

a second layer comprising second transistors, said second transistors consisting essentially of mono-crystalline material, said second layer overlying said first metal layer,

wherein said first metal layer comprises aluminum or copper, and

wherein said second layer is less than one micron in thickness, and

a third layer comprising third transistors, said third transistors consisting essentially of mono-crystalline material,

wherein said third layer substantially overlays said first metal layer, and

wherein said second transistors are N type and said third transistors are P type, and

Complimentary Metal-Oxide-Semiconductor (CMOS) logic cells comprising connections between said second transistors and said third transistors.

21. A semiconductor device according to claim 20 wherein at least one of said second transistors is a recessed channel array transistor.

22. A semiconductor device according to claim 20 wherein at least one of said second transistors is a junction-less transistor.

23. A semiconductor device according to claim 20 wherein at least one of said second transistors is formed by a gate replacement process.

24. A semiconductor device according to claim 20 wherein said second transistors are substantially horizontally oriented transistors.

25. A semiconductor device according to claim 20 wherein said device is part of a mobile system.

26. A semiconductor device according to claim 20 wherein at least one portion of said first transistors and at least one portion of said second transistors are processed following a common lithography step.

27. A semiconductor device according to claim 20 wherein at least a portion of said second transistors overlays at least a portion of said first transistors.

28. A semiconductor device according to claim 20,

wherein at least said first mono-crystallized layer or said first metal layer comprises a first alignment mark,

wherein said second layer comprises a second alignment mark and at least one connection path between said first transistors and said second transistors, and

wherein said path comprises a via aligned in a first direction to said first alignment mark and in a second direction to said second alignment mark.

29. A semiconductor device according to claim 20 wherein the mono-crystalline material of said second layer has a different crystal orientation than the mono-crystalline material of said third layer.

30. A semiconductor device comprising;

a first mono-crystallized layer comprising

first transistors, and

a first metal layer forming at least a portion of connections between said first transistors, and

a second layer comprising second transistors, said second transistors consisting essentially of mono-crystalline material, said second layer overlying said first metal layer,

wherein said first metal layer comprises aluminum or copper,

wherein said second layer is less than one micron in thickness,

wherein at least said first mono-crystallized layer or said first metal layer comprises first alignment mark,

wherein said second layer comprises a second alignment mark and at least one connection path between said first transistors and said second transistors, and

wherein said at least one connection path comprises a via aligned in a first direction to said first alignment mark and in a second direction to said second alignment mark.

31. A semiconductor device according to claim 30 wherein at least one of said second transistors is a recessed channel array transistor.

32. A semiconductor device according to claim 30 wherein at least one of said second transistors is a junction-less transistor.

33. A semiconductor device according to claim 30 wherein at least one of said second transistors is formed by a gate replacement process.

34. A semiconductor device according to claim 30 wherein said second transistors are substantially horizontally oriented transistors.

35. A semiconductor device according to claim 30 wherein said device is part of a mobile system.

36. A semiconductor device according to claim 30 wherein said second transistors comprise logic cells.

37. A semiconductor device according to claim 30 wherein said second transistors comprise memory bit cells forming at least one memory structure.