ENHANCED ATOMIC LAYER DEPOSITION

• US 20110108929A1
• Filed: 01/14/2011
• Published: 05/12/2011
• Est. Priority Date: 08/26/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Derderian, Garo J., Meng, Shuang, Sandhu, Gurtej Singh
• Granted Patent: US 8,362,576 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: C23C 16/45542 Plasma being used non-continuously during the ALD reactions
• CPC Class Codes: C23C 16/515 using pulsed discharges
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF₅ and NE₃. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Claims

1. A transistor comprising:

a plurality of electrodes, wherein at least one of the plurality of electrodes is a field electrode; and

a refractory metal insulator adjacent the field electrode, wherein the insulator is configured to reduce a depletion width in a region adjoining the insulator absent a voltage applied to the field electrode.

2. The transistor of claim 1, wherein the insulator includes tantalum nitride.

3. The transistor of claim 2, wherein the insulator has a resistivity of about 2500 μ

Ohms-cm.

4. The transistor of claim 2, wherein the electrode includes copper.

5. The transistor of claim 1, wherein the insulator includes less than 10% fluorine.

6. The transistor of claim 1, wherein the insulator includes silicon impurities of less than about 5%.

7. The transistor of claim 1, wherein the electrode includes copper and the insulator includes tantalum.

8. A transistor comprising:

a plurality of electrodes, wherein at least one of the plurality is a field electrode; and

a refractory metal insulator adjacent the field electrode, wherein the insulator layer includes a plurality of thin layers, the insulator being configured to reduce a depletion width in a region adjoining the insulator absent a voltage applied to the field electrode.

9. The transistor of claim 8, wherein the plurality of thin layers are atomic layer deposition layers.

10. The transistor of claim 8, wherein the plurality of thin layers each include a thickness of less than 1 angstrom.

11. The transistor of claim 8, wherein the plurality of thin layers each include tantalum nitride.

12. The transistor of claim 11, wherein the plurality of thin layers each includes impurities of less than 10% fluorine.

13. The transistor of claim 12, wherein the plurality of thin layers each includes silicon impurities of less than about 5%.

14. The transistor of claim 13, wherein the electrode includes copper.

15. The transistor of claim 11, wherein the tantalum nitride includes a Ta:

N ratio of about 1;

1.