Integrated Circuit Die Stacks With Translationally Compatible Vias

• US 20110108972A1
• Filed: 11/12/2009
• Published: 05/12/2011
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Kyu-Hyoun, Foster, Jimmy G. SR.
• Granted Patent: US 8,258,619 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/19051 Impedance matching structure [e.g. balun]

Abstract

An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

Claims

1. An integrated circuit die stack comprising:

a first die mounted upon a substrate, the first die comprising pass-through vias (‘

PTVs’

), each PTV comprising a conductive pathway through the first die with no connection to any circuitry on the first die; and

a second die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die so that the PTVs in the first die connect conductors from the substrate through the first die to the TSVs in the second die, each TSV on the second die comprising a conductive pathway through the second die that is also connected to electronic circuitry on the second die, the TSVs and PTVs disposed upon each identical die with the positions of the TSVs and PTVs on each identical die translationally compatible with respect to the TSVs and PTVs on the other identical die so that the second die'"'"'s shift in position aligns PTVs in the first die with TSVs in the second die.

2. The die stack of claim 1 wherein the conductors from the substrate comprise power lines, common lines, and signal lines.

3. The die stack of claim 1 further comprising:

an interface die mounted upon the substrate between the substrate and the first die splitting and connecting a same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die.

4. The die stack of claim 2 further comprising:

the interface die multiplexing and demultiplexing the same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die, the signal lines on the substrate, to the PTVs, and to the TSVs all operating at a same clock speed.

5. The die stack of claim 2 further comprising:

the interface die operating the signal lines on the substrate at a first clock speed and the signals lines to the PTVs and to the TSVs at a second clock speed, the first clock speed sufficiently faster than the second clock speed to fit onto the signal lines of the substrate all communications between the interface die and the PTVs and the TSVs

6. The die stack of claim 1 further comprising:

a first substack mounted upon the substrate, the first substack comprising two or more dies identical to the first die, each of the dies in the first substack stacked upon one another with no shift in position with respect to one another; and

a second substack comprising two or more dies identical to the dies in the first substack, each of the dies in the second substack stacked upon one another with no shift in position with respect to one another, the entire second substack shifted in position with respect to the first substack and mounted upon the first substack so that PTVs in the first substack connect the conductors from the substrate through the first substack to TSVs in the second substack.

7. A method of manufacturing an integrated circuit die stack comprising:

fabricating a plurality of identical integrated circuit dies, each die comprising pass-through-vias (‘

PTVs’

) and through-silicon-vias (‘

TSVs’

) disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translational compatible with respect to the TSVs and PTVs on any other identical die, each PTV comprising a conductive pathway through a die with no connection to any circuitry on the die, each TSV comprising a conductive pathway through a die that is also connected to electronic circuitry on the die;

mounting a first one of the identical integrated circuit dies upon a substrate;

shifting in position with respect to the first die a second one of the identical integrated circuit dies, aligning PTVs in the first die with TSVs in the second die; and

mounting the second die upon the first die with the PTVs in the first die connecting conductors from the substrate through the first die to TSVs in the second die.

8. The method of claim 7 wherein the conductors from the substrate comprise power lines, common lines, and signal lines.

9. The method of claim 7 further comprising:

mounting an interface die upon the substrate between the substrate and the first die, the interface die splitting and connecting a same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die.

10. The method of claim 7 further comprising:

mounting an interface die upon the substrate between the substrate and the first die, the interface die multiplexing and demultiplexing a same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die, the signal lines on the substrate, to the PTVs, and to the TSVs all operating at a same clock speed.

11. The method of claim 7 further comprising:

mounting an interface die upon the substrate between the substrate and the first die, the interface die multiplexing and demultiplexing a same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die, the substrate operating the signal lines on the substrate at a first clock speed and the interface die operating the signal lines to the PTVs and to the TSVs at a second clock speed, the first clock speed sufficiently faster than the second clock speed to fit onto the signal lines of the interface die all communications between the substrate and the PTVs and the TSVs.

12. The method of claim 7 further comprising:

creating a first substack by stacking upon one another, with no shift in position with respect to one another, two or more of the identical dies;

mounting the first substack upon the substrate;

creating a second substack by stacking upon one another, with no shift in position with respect to one another, an additional two or more of the identical dies;

shifting in position the entire second substack with respect to the first substack, aligning PTVs in the first substack with TSVs in the second substack; and

mounting the second substack on the first substack so that PTVs in the first substack connect the conductors from the substrate through the first substack to TSVs in the second substack, the TSVs in the second substack driving active circuitry in the dies of the second substack.

13. A method of operation for an integrated circuit die stack comprising:

transmitting an alternating current signal from a substrate through a first die mounted upon the substrate to electronic circuitry in a second die in the die stack, the second die identical to the first die, shifted in position with respect to the first die, and mounted upon the first die;

conducting, by the first die, the signal through pass-through vias (‘

PTVs’

) in the first die toward the second die, each PTV comprising a conductive pathway through the first die with no connection to any circuitry on the first die; and

conducting, by the second die, the signal through silicon vias (‘

TSVs’

) in the second die to the electronic circuitry, each TSV in the second die comprising a conductive pathway through the second die that is also connected to the electronic circuitry on the second die, wherein the TSVs and PTVs are disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die so that the second die'"'"'s shift in position aligns PTVs in the first die with TSVs in the second die, and the PTVs in the first die connect signal lines from the substrate through the first die to the TSVs in the second die.

14. The method of claim 13 wherein the conductors from the substrate comprise power lines, common lines, and signal lines.

15. The method of claim 13 further comprising:

conducting the signal through an interface die mounted upon the substrate between the substrate and the first, the interface die splitting and connecting a same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die.

16. The method of claim 15 further comprising:

multiplexing and demultiplexing by the interface die the same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die, the signal lines on the substrate, to the PTVs, and to the TSVs all operating at a same clock speed.

17. The method of claim 15 further comprising:

multiplexing and demultiplexing by the interface die the same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die, including operating by the substrate the signal lines on the substrate at a first clock speed and operating by the interface die signal lines to the PTVs and to the TSVs at a second clock speed, the first clock speed sufficiently faster than the second clock speed to fit onto the signal lines of the interface die all communications between the substrate and the PTVs and the TSVs.

18. The method of claim 13 wherein:

transmitting an alternating current signal from a substrate further comprises transmitting the signal through a first substack mounted upon the substrate to electronic circuitry in a second substack in the die stack, the first substack comprising two or more identical dies, each of the dies in the first substack stacked upon one another with no shift in position with respect to one another, the second substack comprising two or more dies identical to the dies in the first substack, each of the dies in the second substack stacked upon one another with no shift in position with respect to one another, the entire second substack shifted in position with respect to the first substack and mounted upon the first substack so that PTVs in the first substack align with TSVs in the second substack and connect the signal lines from the substrate through the first substack to TSVs in the second substack;

conducting the signal through PTVs further comprises conducting the signal by the first substack through PTVs in the first substack, the PTVs comprising conductive pathways through the first substack with no connection to any circuitry in the first substack; and

conducting the signal through TSVs further comprises conducting the signal by the second substack through TSVs in the second substack to electronic circuitry in the second substack, TSVs in the second substack comprising conductive pathways through the second substack that are also connected to electronic circuitry in the second substack.