SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110109351A1
• Filed: 11/03/2010
• Published: 05/12/2011
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: MIYAKE, Hiroyuki, YAMAZAKI, Shunpei, KOYAMA, Jun
• Granted Patent: US 9,093,328 B2
• Time in Patent Office: Days
• US Class Current: 327/109
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/13069 Thin film transistor [TFT]

Abstract

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Claims

1. A semiconductor device comprising:

a first transistor over a substrate; and

a second transistor over the substrate, the first transistor and the second transistor each comprising;

a first electrode layer;

a first insulating film over the first electrode layer;

an oxide semiconductor layer over the first insulating film;

a second electrode layer on the oxide semiconductor layer, the second electrode layer having a first end portion overlapping with the first electrode layer;

a third electrode layer on the oxide semiconductor layer, the third electrode layer having a second end portion overlapping with the first electrode layer;

a second insulating film including an oxide insulating film, the oxide insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer; and

a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and the second insulating film interposed therebetween,

wherein a first region including a surface portion of the oxide semiconductor layer comprises a crystalline region, and

wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.

2. The semiconductor device according to claim 1, wherein the first transistor and the second transistor each further comprising a second region of the oxide semiconductor layer comprising an amorphous region or a mixture region of amorphousness and microcrystals.

3. An inverter circuit comprising the semiconductor device according to claim 1, wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

4. A display device comprising the semiconductor device according to claim 1, wherein the semiconductor device includes a pixel portion and a driver circuit portion which drives the pixel portion.

5. A driving method of the semiconductor device according to claim 1,

wherein the first electrode layer is operated as a main gate electrode in the first transistor, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor.

6. A driving method of the inverter circuit according to claim 3,

wherein the fourth electrode layer is operated as a main gate electrode in the depletion transistor, and

wherein the fourth electrode layer is operated as a main gate electrode in the enhancement transistor.

7. A driving method of the display device according to claim 4,

wherein the first electrode layer is operated as a main gate electrode in the first transistor included in the pixel portion, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor included in the driver circuit portion.

8. A method for manufacturing a first transistor and a second transistor of a semiconductor device comprising the steps of:

forming a first electrode layer;

forming a first insulating film over the first electrode layer;

forming an oxide semiconductor layer over the first insulating film;

performing dehydration or dehydrogenation on the oxide semiconductor layer, so that a crystalline region is formed in a first region including a surface portion of the oxide semiconductor layer;

forming a second electrode layer and a third electrode layer on the oxide semiconductor layer, the second electrode layer having a first end portion overlapping with the first electrode layer, and the third electrode layer having a second end portion overlapping with the first electrode layer;

forming a second insulating film including an oxide insulating film, the oxide insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer; and

forming a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and the second insulating film interposed therebetween,

wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV, and

wherein the first transistor and the second transistor are formed over a substrate.

9. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 8, wherein the first transistor and the second transistor each further comprising a second region of the oxide semiconductor layer comprising an amorphous region or a mixture region of amorphousness and microcrystals.

10. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 8,

wherein an inverter circuit comprising the semiconductor device, and

wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

11. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 8,

wherein a display device comprising the semiconductor device, and

wherein the semiconductor device includes a pixel portion and a driver circuit portion which drives the pixel portion.

12. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 8,

wherein the first electrode layer is operated as a main gate electrode in the first transistor, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor.

13. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 10,

wherein the fourth electrode layer is operated as a main gate electrode in a depletion transistor;

and

wherein the fourth electrode layer is operated as a main gate electrode in an enhancement transistor.

14. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 11,

wherein the first electrode layer is operated as a main gate electrode in the first transistor included in a pixel portion, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor included in a driver circuit portion.