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STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING

  • US 20110110149A1
  • Filed: 11/23/2010
  • Published: 05/12/2011
  • Est. Priority Date: 01/19/2005
  • Status: Active Grant
First Claim
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1. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure within the integrated circuit for writing to the memory cells comprising:

  • a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;

    a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and

    a bit line driver receiving the controlled current and an unselected bit line voltage, the bit line driver selecting between providing to a bit line the controlled current and the unselected bit line voltage in response to a driver control signal, the bit line providing the controlled current to at least one of the memory cells comprising phase change memory elements.

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