WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME

• US 20110110163A1
• Filed: 01/14/2011
• Published: 05/12/2011
• Est. Priority Date: 01/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yamada, Shigekazu
• Granted Patent: US 8,238,165 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.

Claims

1. A method of applying a voltage on word lines of an array of non-volatile memory cells in a non-volatile memory device comprising:

selecting one of at least two voltages to provide as an output signal depending upon the nature of an operation being performed by the non-volatile memory device; and

selectively applying the output signal to the respective word line of a memory cell in the non-volatile memory device.

2. The method of claim 1 wherein the act of selectively applying the output signal to the respective word line comprises selectively applying the output signal to the respective word line responsive to receiving a row address.

3. The method of claim 1 wherein the act of selecting one of at least two voltages to provide as an output signal comprises:

supplying a programming voltage as the output signal during a programming operation;

supplying one of at least two bias voltages as the output signal during a read operation; and

supplying one of at least two enable voltages as the output signal to enable either a programming operation or a reading operation.

4. The method of claim 3 further comprising:

storing at least one bit of data from a predetermined number of data bits in a selected row of memory cells during a programming operation; and

supplying one of a plurality of bias voltages during a reading operation to read the stored at least one bit of data, wherein each one of the plurality of bias voltages corresponds to each of the predetermined number of data bits.

5. The method of claim 1 further comprising gradually discharging the filtered output voltage signal from the respective word line after the memory operation is complete.

6. The method of claim 1 further comprising disabling the word lines when the array of the non-volatile memory cells are inactive.

7. A method of driving a voltage signal on each word line of an array of non-volatile memory cells in a non-volatile memory comprising:

filtering a voltage to generate a filtered output voltage signal; and

selectively applying the filtered output voltage signal to one of a plurality of word lines in the non-volatile memory device.

8. The method of claim 7 wherein the filtered voltage comprises one of at least two different voltages.

9. The method of claim 8 wherein the at least two different voltages correspond to different levels of charge stored in the non-volatile memory cells connected to a word line to which the at least two different voltages are coupled.

10. The method of claim 7 further comprising gradually discharging the filtered output voltage signal from the respective word lines of the memory cells.

11. The method of claim 7 wherein the act of filtering the selected one of at least two voltages comprises selecting a combination of low pass filters from a predetermined number of low pass filters to configure a delay time from a predetermined range of delay times corresponding to the predetermined number of low pass filters.

12. The method of claim 7 further comprising disabling the word lines when the array of the non-volatile memory cells are inactive.