Non-volatile memory systems and methods including page read and/or configuration features
6 Assignments
0 Petitions
Accused Products
Abstract
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
103 Citations
153 Claims
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1-88. -88. (canceled)
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89. A method comprising:
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reading a fuse non-volatile memory location for configuration data in response to a page read command; storing said configuration data in a volatile memory location; and using the configuration data to initiate a page read sequence for a memory.
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90. A method comprising:
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reading a fuse non-volatile memory location for configuration data in response to a page program command; storing said configuration data in a volatile memory location; and using the configuration data to initiate a page programming sequence for a memory.
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91-126. -126. (canceled)
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127. A system comprising:
one or more circuits configured to; read a fuse non-volatile memory location for configuration data in response to a page read command; store the configuration data in a volatile memory location; and use the configuration data to initiate a page read sequence for a memory. - View Dependent Claims (129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153)
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128. A system comprising:
one or more circuits configured to; read a fuse non-volatile memory location for configuration data in response to a page program command; store the configuration data in a volatile memory location; and using the configuration data to initiate a page programming sequence for a memory.
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139. The system of 127 wherein the system is configured to:
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couple a reference array to reference memory subarrays; and provide stored reference signals used for programming reference memory cells, the stored reference signals corresponding to detected reference signals.
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Specification