Bimetallic integrated on-chip thermocouple array

• US 20110110396A1
• Filed: 09/20/2010
• Published: 05/12/2011
• Est. Priority Date: 09/18/2009
• Status: Active Grant

• Current Assignee: Northwestern University
• Original Assignee: Northwestern University
• Inventors: Zhou, Chuanle, Grayson, Matthew A., Long, Jieyi, Memik, Seda, Klock, Andrea Grace
• Granted Patent: US 8,517,605 B2
• Time in Patent Office: Days
• US Class Current: 374/178
• CPC Class Codes: G01K 1/026 arrangements for monitoring a plurality of temperatures, e.g. by multiplexing
• CPC Class Codes: G01K 7/028 using microstructures, e.g. made of silicon
• CPC Class Codes: H10N 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00

Abstract

An integrated circuit chip is defined by a stack of several interconnected layers. The integrated circuit chip includes at least two layers of dissimilar metal patterned to define an array of integrated bimetallic thermocouples.

Claims

1. An apparatus, comprising:

a semiconductor integrated circuit chip defined by a stack of several interconnected layers including at least two layers of dissimilar metal patterned to define an array of integrated bimetallic thermocouples spaced apart from one another, each of the thermocouples being operatively connected to a thermal management circuit defined by the integrated circuit chip.

2. The apparatus of claim 1, wherein at least a portion of the integrated circuit chip defining a logic unit.

3. The apparatus of claim 2, wherein the logic unit is a microprocessor.

4. The apparatus of claim 1, wherein one or more of the layers being of a semiconductor type.

5. The apparatus of claim 1, wherein one or more of the layers being of a dielectric type.

6. The apparatus of claim 1, wherein the thermal management circuit including means for reducing elevated operation temperatures.

7. The apparatus of claim 1, wherein at least a portion of the integrated circuit chip defining integrated circuitry having field effect transistors of opposite polarity.

8. The apparatus of claim 1, wherein at least a portion of the integrated circuit chip defining a thermal reference circuit.

9. The apparatus of claim 8, wherein the thermal reference circuit is structured to minimize error in temperature readings.

10. The apparatus of claim 1, wherein at least one of the first type of metal and the second type of metal includes copper.

11. A method, comprising:

preparing circuitry of an integrated circuit device from a number of layers of different composition, the layers including at least two metallic layers of dissimilar metals;

patterning the metallic layers to define a number of spaced apart bimetallic thermocouple junctions positioned along the circuitry; and

operatively coupling the thermocouple junctions to a thermal management device for the integrated circuit device.

12. The method of claim 11, further comprising:

defining a logic device with the circuitry.

13. The method of claim 12, wherein the logic device is a microprocessor.

14. The method of claim 11, wherein one or more of the layers being of a semiconductor type.

15. The method of claim 11, wherein one or more of the layers being a dielectric type.

16. The method of claim 11, further comprising:

defining the thermal management device with the circuitry.

17. The method of claim 11, further comprising:

providing a thermal reference device for the thermocouples.

18. The method of claim 17, wherein the thermal reference device is formed as part of the thermal management device.

19. The method of claim 11, further comprising:

reducing elevated operation temperatures.

20. The method of claim 11, wherein at least a portion of the circuitry being defined with field effect transistors of opposite polarity.

21. The method of claim 11, wherein at least one of the first type of metal and the second type of metal including copper.

22. The method of claim 11, wherein the patterning step is performed by lithography.

23. The method of claim 17, wherein the thermal reference device is structured to minimize error in temperature readings.

24. A method, comprising:

providing an integrated circuit chip having a patterned array of integrated bimetallic thermocouples spaced apart from one another;

calculating, with a thermal management circuit of the integrated circuit chip, a temperature reading of a region of the integrated circuit chip; and

performing an action in response to the temperature reading.

25. The method of claim 24, wherein the action includes stopping all processing on the integrated circuit chip except for performing subsequent temperature readings.

26. The method of claim 24, wherein the action includes reducing a processing speed of the integrated circuit chip.

27. The method of claim 24, wherein the action includes preventing processing in certain regions of the integrated circuit chip where the temperature reading is outside of a predetermined temperature range.

28. The method of claim 24, wherein the action includes changing an operating characteristic of the integrated circuit chip.

29. The method of claim 24, further comprising:

resuming to normal processing after a subsequent temperature reading is at or near a predetermined value.

30. The method of claim 24, wherein the action includes alerting a user when the temperature reading is outside of a predetermined range.