DATA STORAGE SYSTEM AND METHOD

• US 20110113281A1
• Filed: 05/20/2010
• Published: 05/12/2011
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Zhang, Bo, Chen, Liang, Chai, Honggang
• Granted Patent: US 8,347,180 B2
• Time in Patent Office: Days
• US Class Current: 714/6.12
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A data storage system and method are disclosed. The data storage system includes a first memory, a controller, a counting module, and a checking and correcting module. Copyback operations are performed in the first memory. The controller couples the first memory to the counting module and the checking and correcting module. The counting module provides a counting operation for the copyback operations at different logic addresses of the first memory and, according to a counting result of the counting operation, determines whether a checking and correcting requirement has been satisfied by any of the logic addresses. The checking and correcting module receives data read out from the first memory, wherein the received data corresponds to a satisfying logic address, and checks, or checks and corrects the received data to correct the first memory accordingly.

Claims

1. A data storage system, comprising

a first memory, where copyback operations are performed;

a controller, coupling the first memory to a counting module and a checking and correcting module;

the counting module, providing a counting operation for copyback operations at different logic addresses of the first memory and, based on a counting result of the counting operation, determining whether a checking and correcting requirement has been satisfied by any of the logic addresses; and

the checking and correcting module, receiving data read out from the first memory, wherein the received data corresponds to a satisfying logic address which satisfies the checking and correcting requirement, and checking, or checking and correcting the received data to correct the first memory accordingly.

2. The data storage system as claimed in claim 1, wherein the controller is further coupled to a second memory, and the second memory is operative to temporarily store the counting result of the counting operation.

3. The data storage system as claimed in claim 1, wherein the counting operation counts the times of the copyback operations occurring at each of the logic addresses.

4. The data storage system as claimed in claim 3, wherein the logic address at which more than a predetermined times of copyback operations have occurred is determined as the satisfying logic address that satisfies the checking and correcting requirement.

5. The data storage system as claimed in claim 1, wherein the counting operation sets a frequency indicator of each logic address according to a frequency indicator changing probability every time the copyback operation is performed at the corresponding logic address.

6. The data storage system as claimed in claim 5, wherein each frequency indicator includes one-bit information.

7. The data storage system as claimed in claim 5, wherein when any of the frequency indicators is set to a predetermined value, the corresponding logic address is determined as the satisfying logic address that satisfies the checking and correcting requirement.

8. The data storage system as claimed in claim 1, wherein:

the checking and correcting module determines whether the received data is incorrect, then corrects the received data and writes the corrected received data to a free physical space of the first memory for data refreshing if the received data is incorrect.

9. The data storage system as claimed in claim 1, wherein:

before the received data is read out from the first memory, the controller determines whether a next copyback operation is required at the satisfying logic address;

if the next copyback operation is required at the satisfying logic address, the checking and correcting module determines whether the received data is incorrect, then corrects the received data and writes the corrected received data to a free physical space of the first memory if the received data is incorrect, or writes the received data to the free physical space of the first memory if the received data is correct.

10. The data storage system as claimed in claim 9, wherein the next copyback operation is suspended.

11. The data storage system as claimed in claim 1, wherein the first memory is a NAND flash.

12. A data storage method, for a first memory where copyback operations are performed, wherein the method comprises:

providing a counting operation for copyback operations at different logic addresses of the first memory;

determining whether a checking and correcting requirement has been satisfied by any of the logic addresses according to a counting result of the counting operation; and

receiving data read out from the first memory, wherein the received data corresponds to a satisfying logic address which satisfies the checking and correcting requirement, and checking, or checking and correcting the received data to refresh the first memory accordingly.

13. The data storage method as claimed in claim 12, wherein after the step of checking, or checking and correcting, the counting result of the satisfying logic address is reset.

14. The data storage method as claimed in claim 12, wherein the counting operation counts the times of the copyback operations occurring at each of the logic addresses.

15. The data storage method as claimed in claim 14, wherein the logic address at which more than a predetermined times of copyback operations have occurred is determined as the satisfying logic address that satisfies the checking and correcting requirement, where N is a number.

16. The data storage method as claimed in claim 12, wherein the counting operation sets a frequency indicator of each logic address according to a frequency indicator changing probability every time the copyback operation is performed at the corresponding logic address.

17. The data storage method as claimed in claim 16, wherein when any of the frequency indicators is set to a predetermined value, the corresponding logic address is determined as the satisfying logic address that satisfies the checking and correcting requirement.

18. The data storage method as claimed in claim 12, wherein when the step of checking determines whether the received data is incorrect, the step of correcting corrects the received data and writes the corrected received data to a free physical space of the first memory if the received data is incorrect.

19. The data storage method as claimed in claim 12, wherein:

before the received data is read out from the first memory, determining whether a next copyback operation is required at the satisfying logic address;

if the next copyback operation is required at the satisfying logic address, the step of checking determines whether the received data is incorrect, the step of correcting corrects the received data and writes the corrected received data to a free physical space of the first memory if the received data is incorrect, or writes the received data to the free physical space of the first memory if the received data is correct.

20. The data storage method as claimed in claim 19, wherein the next copyback operation is suspended.