VOLTAGE GENERATOR CIRCUIT, DIGITAL-TO-ANALOG CONVERTER, RAMP GENERATOR CIRCUIT, ANALOG-TO-DIGITAL CONVERTER, IMAGE SENSOR SYSTEM, AND METHOD FOR GENERATING VOLTAGE

• US 20110114827A1
• Filed: 01/24/2011
• Published: 05/19/2011
• Est. Priority Date: 08/18/2009
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: YAMAOKA, Yuusuke, Nishimura, Kazuko
• Granted Patent: US 8,093,543 B2
• Time in Patent Office: Days
• US Class Current: 250/214.R
• CPC Class Codes: H03K 4/026 using digital techniques
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp
• CPC Class Codes: H03M 1/58 Non-linear conversion
• CPC Class Codes: H03M 1/664 Non-linear conversion not otherwise provided for in subgroups of H03M1/66
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A resistor-ladder voltage generator circuit is provided, which controls so that k switches among consecutive (k+1) switches out of a plurality of switches connected to the resistor ladder circuit are simultaneously set to an ON state, and which temporally switches the value of k. This allows voltage waveforms having different slopes to be arbitrarily obtained, ranging from a voltage waveform having a small slope to a voltage waveform having a large slope, thereby improving the resolution of a generated voltage waveform without increasing the numbers of resistors and switches, while A/D conversion time is not increased even if the number of bits is increased. In addition, by using this voltage generator circuit as a ramp generator circuit, and by dynamically switching the slope of the ramp wave, acceleration of an image sensor is achieved.

Claims

1. A voltage generator circuit, comprising:

a resistor ladder circuit configured to receive a predetermined voltage or a predetermined current, and to generate a plurality of reference voltages different from one another;

a plurality of switches corresponding to a plurality of taps of the resistor ladder circuit, each of which has one end connected to the tap corresponding thereto and the other end connected to an output node; and

a switch control circuit configured to control on-off states of the plurality of switches so that k (k is an integer greater than or equal to one) switches among consecutive (k+1) switches out of the plurality of switches are set to an ON state, and capable of switching the value of k.

2. A D/A converter, comprising:

the voltage generator circuit of claim 1,

wherein

the switch control circuit receives a digital code and controls the on-off states of the plurality of switches according to the digital input code, and

an analog voltage output is obtained from the output node.

3. A ramp generator circuit, comprising:

the voltage generator circuit of claim 1,

wherein

the switch control circuit of the voltage generator circuit switches the on-off states of the plurality of switches according to a predetermined timing signal, and

a ramp-wave output is obtained the output node.

4. An A/D converter, comprising:

a reference signal generation section configured to generate a reference signal for converting analog signals into digital signals;

a comparison section configured to compare the analog signals with the reference signal;

a counter section configured to perform a counting operation in parallel with a comparison operation in the comparison section, and to hold a count value when the output of the comparison section is inverted, in order to obtain digital signals corresponding to the analog signals; and

a correction section configured to correct an output from the counter section,

wherein

the reference signal generation section includes the ramp generator circuit of claim 3, switches the value of k, and sets the slope of the reference signal in multiple stages according to the magnitude of the reference signal, and

the correction section corrects the output of the counter section according to the slope of the reference signal.

5. The A/D converter of claim 4, wherein

the correction section includes

a delay measurement section configured to measure a delay from when the reference signal is output from the reference signal generation section until the reference signal is input to the comparison section, and to feed back the measured delay to the correction to the output of the counter section.

6. An image sensor system, comprising:

a pixel section, in which a plurality of pixels each having a light receiving element which outputs a signal depending on the amount of incident light are arranged in a two-dimensional matrix;

a vertical scan circuit configured to sequentially select pixels from the pixels on a line-by-line basis;

the A/D converter of claim 5 for converting an analog signal from each of the pixels to a digital signal;

a horizontal scan circuit configured to sequentially select an output of the A/D converter on a column-by-column basis; and

a communication timing control section configured to generate clock signals and control signals, and to control at least the A/D converter.

7. The image sensor system of claim 6, wherein

the delay measurement section of the A/D converter measures a time for a ramp wave generated in the ramp generator circuit to reach a preset reference voltage, and calculates the delay by comparing the measured time with a reference time, during a predetermined initialization period.

8. The image sensor system of claim 7, wherein

the time measurement by the delay measurement section is performed on each column of the pixel section, multiple times in total, and the times measured for the respective columns are averaged to obtain the delay.

9. The image sensor system of claim 7, wherein

the time measurement by the delay measurement section is performed for all the columns of the pixel section at one time, and the times measured for all the columns are averaged to obtain the delay.

10. A method for generating a voltage in a voltage generator circuit which includes a resistor ladder circuit configured to generate a plurality of reference voltages different from one another, and a plurality of switches corresponding to a plurality of taps of the resistor ladder circuit, each of which has one end connected to the tap corresponding thereto and the other end connected to an output node,

wherein

on-off states of the plurality of switches are controlled so that k (k is an integer greater than or equal to one) switches among consecutive (k+1) switches out of the plurality of switches are set to an ON state, and the value of k is sequentially switched.