SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110114943A1
• Filed: 11/12/2010
• Published: 05/19/2011
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,410,002 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer formed over a substrate;

a source electrode and a drain electrode formed over the oxide semiconductor layer;

the source electrode and the drain electrode, each is electrically connected to the oxide semiconductor layer;

a gate insulating layer formed over the oxide semiconductor layer, the source electrode and the drain electrode; and

a gate electrode formed over the gate insulating layer,

wherein the source electrode and the drain electrode include an oxide region formed by oxidizing a side surface of the source electrode and the drain electrode.

2. The semiconductor device according to claim 1, wherein the oxide region of the source electrode and the drain electrode is formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

3. The semiconductor device according to claim 1, further comprising a protective insulating layer over the source electrode and the drain electrode, the protective insulating layer having a substantially same planar shape as a planar shape of the source electrode and the drain electrode.

4. The semiconductor device according to claim 1, wherein a hydrogen concentration of the oxide semiconductor layer is 5×

10¹⁹/cm³ or less.

5. The semiconductor device according to claims 1, wherein an off-state current is 1×

10<sup>−

13</sup> A or less.

6. A manufacturing method of a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

oxidizing a side surface of the source electrode and the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer, the source electrode, and the drain electrode after oxidizing the side surface of the source electrode and the drain electrode; and

forming a gate electrode over the gate insulating layer.

7. The manufacturing method of a semiconductor device according to claim 6, wherein the side surface of the source electrode and the drain electrode is oxidized by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

8. The manufacturing method of a semiconductor device according to claim 6, further comprising the step of forming a protective insulating layer having a substantially same planar shape as a planar shape of the source electrode and the drain electrode over the source electrode and the drain electrode.

9. The manufacturing method of a semiconductor device according to claims 6, wherein an off-state current is made 1×

10<sup>−

13</sup> A or less by making a hydrogen concentration of the oxide semiconductor layer 5×

10¹⁹/cm³ or less.