THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A three-dimensional semiconductor memory device comprising:
- a substrate comprising a cell array region including a pair of sub-cell regions and a strapping region between the pair of sub-cell regions;
a plurality of sub-gates sequentially stacked on the substrate in each of the sub-cell regions, each of the sub-gates including an extension extending laterally into the strapping region;
a vertical-type channel pattern successively penetrating the stacked sub-gates within each of the sub-cell regions; and
interconnections electrically connected to the extensions of the stacked sub-gates, respectively, each of the interconnections being electrically connected to the extensions of sub-gates which are disposed in the pair of the sub-cell regions, respectively, and are located at the same level.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.
-
Citations
21 Claims
-
1. A three-dimensional semiconductor memory device comprising:
-
a substrate comprising a cell array region including a pair of sub-cell regions and a strapping region between the pair of sub-cell regions; a plurality of sub-gates sequentially stacked on the substrate in each of the sub-cell regions, each of the sub-gates including an extension extending laterally into the strapping region; a vertical-type channel pattern successively penetrating the stacked sub-gates within each of the sub-cell regions; and interconnections electrically connected to the extensions of the stacked sub-gates, respectively, each of the interconnections being electrically connected to the extensions of sub-gates which are disposed in the pair of the sub-cell regions, respectively, and are located at the same level. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A three-dimensional semiconductor memory device comprising:
-
a substrate comprising a cell array region including a first sub-cell region, a second sub-cell region, and a strapping region interposed between the first and second sub-cell regions; a plurality of first sub-gates being sequentially stacked on the substrate of the first sub-cell region, each of the first sub-gates including an extension extending laterally into the strapping region; a plurality of second sub-gates being sequentially stacked on the substrate of the second sub-cell region, each of the second sub-gates including an extension extending laterally into the strapping region; a first vertical-type channel pattern penetrating the stacked first sub-gates within the first sub-cell regions and a second vertical-type channel pattern penetrating the stacked second sub-gates within the second sub-cell regions; a first bitline and a second bitline electrically connected to top ends of the first and second vertical-type channel patterns, respectively, the first and second bitlines being parallel to each other; and a plurality of strapping lines crossing over the first and second bitlines, wherein each of the strapping lines is electrically connected to the extension of the first sub-gate and the extension of the second sub-gates which are located at the same level. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21-33. -33. (canceled)
Specification