Semiconductor Device Packages with Electromagnetic Interference Shielding

• US 20110115059A1
• Filed: 11/19/2009
• Published: 05/19/2011
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lee, Yuyong, Kim, Seokbong
• Granted Patent: US 8,368,185 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a circuit substrate, an electronic device, an encapsulant, and a conductive coating. The circuit substrate includes a carrying surface, a bottom surface, a lateral surface extending between the carrying surface and the bottom surface, a conductive layer, and a grounding ring. The grounding ring is in a substantially continuous pattern extending along a border of the circuit substrate, is exposed at a lateral surface of the circuit substrate, and is included in the conductive layer. The electronic device is disposed adjacent to the carrying surface and is electrically connected to the conductive layer of the circuit substrate. The encapsulant is disposed adjacent to the carrying surface and encapsulates the electronic device. The conductive coating is applied to the encapsulant and the grounding ring.

Claims

1. A semiconductor device package, comprising:

a circuit substrate including;

a carrying surface;

a bottom surface;

a lateral surface extending between the carrying surface and the bottom surface;

a conductive layer; and

a grounding ring in a substantially continuous pattern extending along a border of the circuit substrate, the grounding ring being exposed at the lateral surface of the circuit substrate and included in the conductive layer;

an electronic device disposed adjacent to the carrying surface and electrically connected to the conductive layer of the circuit substrate;

an encapsulant disposed adjacent to the carrying surface and encapsulating the electronic device; and

a conductive coating applied to the encapsulant and the grounding ring.

2. The semiconductor device package of claim 1, wherein a peripheral portion of the carrying surface is downwardly recessed to form a recessed portion, the recessed portion extending along the border of the circuit substrate and included in the lateral surface of the circuit substrate, and the grounding ring being exposed at the recessed portion.

3. The semiconductor device package of claim 2, wherein the circuit substrate is a multilayer circuit substrate, the recessed portion is downwardly recessed to an inner layer of the circuit substrate, and the conductive layer is located above the inner layer.

4. The semiconductor device package of claim 2, wherein a bottom of the recessed portion is curved.

5. The semiconductor device package of claim 4, wherein the grounding ring is exposed at the curved bottom of the recessed portion.

6. The semiconductor device package of claim 1, wherein a portion of the grounding ring exposed at the lateral surface extends fully around the border of the circuit substrate.

7. The semiconductor device package of claim 6, wherein the conductive coating is applied to substantially all of the portion of the grounding ring exposed at the lateral surface.

8. A semiconductor device package, comprising:

a circuit substrate including;

a first surface;

a second opposing surface; and

a first grounding ring including a first exposed connection surface, the first exposed connection surface disposed between the first surface and the second opposing surface of the circuit substrate, and extending at least fifty percent around the circuit substrate in a first plane substantially parallel to the first surface and the second opposing surface;

an electronic device disposed adjacent to the first surface and electrically connected to the circuit substrate;

an encapsulant disposed adjacent to the first surface and encapsulating the electronic device; and

an electromagnetic interference shield disposed adjacent to the encapsulant and the first exposed connection surface of the first grounding ring.

9. The semiconductor device package of claim 8, wherein the electromagnetic interference shield includes a conformal coating applied to substantially all of the first exposed connection surface of the first grounding ring.

10. The semiconductor device package of claim 9, wherein the first exposed connection surface of the first grounding ring extends fully around the circuit substrate in the first plane.

11. The semiconductor device package of claim 8, wherein the electromagnetic interference shield includes a conformal coating that includes at least one of aluminum, copper, chromium, gold, silver, nickel, tin, and stainless steel.

12. The semiconductor device package of claim 8, wherein the circuit substrate further includes a second grounding ring including a second exposed connection surface, the second exposed connection surface disposed between the first surface and the second opposing surface of the circuit substrate, and extending at least fifty percent around the circuit substrate in a second plane substantially parallel to the first plane.

13. The semiconductor device package of claim 12, wherein the electromagnetic interference shield is applied to substantially all of the second exposed connection surface of the second grounding ring.

14. The semiconductor device package of claim 8, wherein:

the circuit substrate includes a lateral surface extending between the first surface and the second opposing surface of the circuit substrate, the lateral surface including a recessed portion; and

the first exposed connection surface of the first grounding ring is exposed at the recessed portion.

15. The semiconductor device package of claim 14, wherein the recessed portion is curved.

16. A method of forming a semiconductor device package, comprising:

providing a substrate including;

a carrying surface;

a bottom surface; and

a grounding ring;

electrically connecting a semiconductor device to the carrying surface of the substrate;

applying a molding material to the carrying surface of the substrate to form a molded structure covering the semiconductor device;

forming a first set of cutting slits extending through the molded structure and extending partially through the substrate, such that;

(a) a portion of the molded structure covers the semiconductor device;

(b) a portion of a lateral surface of the substrate is exposed; and

(c) a portion of the grounding ring is exposed at the lateral surface;

forming a conductive coating adjacent to the portion of the molded structure covering the semiconductor device, the portion of the lateral surface exposed by the first set of cutting slits, and the portion of the grounding ring exposed by the first set of cutting slits; and

forming a second set of cutting slits extending through the conductive coating and the substrate, such that;

(a) the conductive coating is sub-divided to form an electromagnetic interference shield disposed adjacent to the semiconductor device, the portion of the lateral surface exposed by the first set of cutting slits, and the portion of the grounding ring exposed by the first set of cutting slits;

(b) the substrate is sub-divided to form a substrate unit including a carrying surface, the semiconductor device disposed adjacent to the carrying surface of the substrate unit; and

(c) the substrate unit includes the grounding ring, wherein the grounding ring is in a substantially continuous pattern extending along a border of the substrate unit.

17. The method of claim 16, wherein a width of at least one of the first set of cutting slits is in the range of 300 microns to 500 microns.

18. The method of claim 16, wherein a width of at least one of the second set of cutting slits is in the range of 250 microns to 350 microns.

19. The method of claim 16, wherein the second set of cutting slits is aligned with respect to the first set of cutting slits, and a width of at least one of the second set of cutting slits is less than a width of at least one of the first set of cutting slits.

20. The method of claim 16, wherein at least one of the first set of cutting slits is curved.