Wafer-Level Semiconductor Device Packages with Electromagnetic Interference Shielding

• US 20110115060A1
• Filed: 11/19/2009
• Published: 05/19/2011
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Fan, Chen-Chuan, Chen, Yui-Chi, Yih, Wei-Chi, Chiu, Chi-Tsung, Liao, Kuo-Hsien
• Granted Patent: US 8,378,466 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are wafer-level semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a semiconductor device; (2) a package body covering lateral surfaces of the semiconductor device, a lower surface of the package body and a lower surface of the semiconductor device defining a front surface; (3) a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers including a grounding element that includes a connection surface electrically exposed adjacent to at least one lateral surface of the set of redistribution layers; and (4) an EMI shield disposed adjacent to the package body and electrically connected to the connection surface of the grounding element. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor device package, comprising:

a semiconductor device including (a) a lower surface, (b) lateral surfaces disposed adjacent to a periphery of the semiconductor device, and (c) a contact pad disposed adjacent to the lower surface of the semiconductor device;

a package body covering the lateral surfaces of the semiconductor device, the package body including (a) an upper surface, (b) a lower surface, and (c) lateral surfaces disposed adjacent to a periphery of the package body, the lower surface of the package body and the lower surface of the semiconductor device defining a front surface;

a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers including (a) lateral surfaces disposed adjacent to a periphery of the set of redistribution layers and (b) a grounding element, the grounding element including a connection surface that is electrically exposed adjacent to at least one of the lateral surfaces of the set of redistribution layers; and

an electromagnetic interference shield disposed adjacent to the upper surface of the package body and the lateral surfaces of the package body and electrically connected to the connection surface of the grounding element,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

2. The semiconductor device package of claim 1, wherein the grounding element extends between the contact pad of the semiconductor device and at least one of the lateral surfaces of the set of redistribution layers.

3. The semiconductor device package of claim 2, wherein the set of redistribution layers includes a lower surface, the semiconductor device package further comprises an electrical contact disposed adjacent to the lower surface of the set of redistribution layers, and the grounding element is electrically connected to the electrical contact.

4. The semiconductor device package of claim 3, wherein the electrical contact is laterally disposed outside of the periphery of the semiconductor device.

5. The semiconductor device package of claim 1, wherein the grounding element includes a first portion and a second portion, the first portion is electrically connected to the contact pad of the semiconductor device, and the second portion is disposed adjacent to the periphery of the set of redistribution layers and includes the connection surface.

6. The semiconductor device package of claim 5, wherein the second portion corresponds to a grounding ring.

7. The semiconductor device package of claim 5, wherein the second portion corresponds to a grounding strip.

8. The semiconductor device package of claim 5, wherein the second portion corresponds to a remnant of a grounding via.

9. The semiconductor device package of claim 1, wherein the set of redistribution layers includes a dielectric layer disposed adjacent to the front surface, and the grounding element includes an electrical trace that extends along the dielectric layer.

10. The semiconductor device package of claim 1, wherein the electromagnetic interference shield includes a lateral portion that extends along the lateral surfaces of the set of redistribution layers.

11. The semiconductor device package of claim 10, wherein the set of redistribution layers includes a lower surface, and a lower end of the lateral portion is substantially aligned with the lower surface of the set of redistribution layers.

12. The semiconductor device package of claim 1, wherein the lower surface of the package body is substantially aligned with the lower surface of the semiconductor device.

13. The semiconductor device package of claim 1, wherein the lateral surfaces of the package body are substantially aligned with respective ones of the lateral surfaces of the set of redistribution layers.

14. A semiconductor device package;

comprising;

a semiconductor device including an active surface;

a package body covering the semiconductor device such that the active surface of the semiconductor device is electrically exposed, the package body including exterior surfaces;

a redistribution unit including (a) a dielectric layer disposed adjacent to the active surface of the semiconductor device and defining openings that are aligned with the active surface of the semiconductor device, (b) an electrical trace extending along the dielectric layer and electrically connected to the active surface of the semiconductor device through one of the openings defined by the dielectric layer, and (c) a grounding element extending along the dielectric layer and including a lateral surface disposed adjacent to a periphery of the redistribution unit; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element,

wherein the grounding element provides an electrical, pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

15. The semiconductor device package of claim 14, wherein the grounding element includes a portion that is disposed adjacent to the periphery of the redistribution unit and includes the lateral surface, and the portion corresponds to at least one of a grounding ring, a grounding strip, and a remnant of a grounding via.

16. The semiconductor device package of claim 14, wherein the grounding element is electrically connected to the active surface of the semiconductor device through another one of the openings defined by the dielectric layer.

17. The semiconductor device package of claim 14, wherein the electromagnetic interference shield is a conformal shield that includes at least one of aluminum, copper, chromium, tin, gold, silver, stainless steel, and nickel.

18. The semiconductor device package of claim 14, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer.

19. The semiconductor device package of claim 18, wherein the first layer and the second layer include different electrically conductive materials.

20. The semiconductor device package of claim 14, wherein a thickness of the electromagnetic interference shield is in the range of 1 μ

m to 50 μ

m.

21. The semiconductor device package of claim 14, wherein a thickness of the redistribution unit is in the range of 14 μ

m to 42 μ

m, and a thickness of the grounding element is in the range of 2 μ

m to 6 μ

m.

22. A method of forming a semiconductor device package, comprising:

providing a semiconductor device including an active surface;

applying a molding material to form a molded structure covering the semiconductor device with the active surface of the semiconductor device being at least partially exposed;

forming a redistribution structure adjacent to the active surface of the semiconductor device, the redistribution structure including an electrical interconnect extending laterally within the redistribution structure;

forming cutting slits extending through the molded structure and the redistribution structure, the cutting slits being aligned with the redistribution structure, such that;

(a) the redistribution structure is sub-divided to form a redistribution unit;

(h) the molded structure is sub-divided to form a package body including exterior surfaces; and

(c) a remnant of the electrical interconnect corresponds to a grounding element including an exposed connection surface; and

applying an electromagnetic interference coating to the exterior surfaces of the package body and the connection surface of the grounding element to form an electromagnetic interference shield.

23. The method of claim 22, wherein forming the redistribution structure includes:

applying a dielectric material to the active surface of the semiconductor device to form a dielectric layer adjacent to the active surface of the semiconductor device; and

applying an electrically conductive material to the dielectric layer to form the electrical interconnect extending along the dielectric layer.

24. The method of claim 23, wherein forming the redistribution structure further includes patterning the dielectric material to define an opening in the dielectric layer, and wherein applying the electrically conductive material includes applying the electrically conductive material into the opening to form a grounding via disposed in the opening.

25. The method of claim 24, wherein, subsequent to forming the cutting slits, the grounding element includes a remnant of the grounding via.