SEMICONDUCTOR DEVICE

• US 20110115545A1
• Filed: 11/10/2010
• Published: 05/19/2011
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: WATANABE, Kazunori, KOYAMA, Jun
• Granted Patent: US 8,334,719 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/73 for dc voltages or currents H03K17/722, H03K17/735 take precedence

Abstract

An object is to provide a semiconductor device that can realize a function of a thyristor without complication of the process. A semiconductor device including a memory circuit that stores a predetermined potential by reset operation and initialization operation is provided with a circuit that rewrite data in the memory circuit in accordance with supply of a trigger signal. The semiconductor device has a structure in which a current flowing through the semiconductor device is supplied to a load by rewriting data in the memory circuit, and thus can function as a thyristor.

Claims

1. A semiconductor device comprising:

first to ninth insulated gate transistors;

a capacitor;

a first wiring to which a first high power supply potential is supplied;

a second wiring to which a second high power supply potential is supplied;

a third wiring to which a first low power supply potential is supplied; and

a fourth wiring to which a second low power supply potential is supplied,

wherein a gate of the first insulated gate transistor is electrically connected to an input terminal, a first terminal of the first insulated gate transistor is electrically connected to the third wiring, and a second terminal of the first insulated gate transistor is electrically connected to a first terminal of the second insulated gate transistor,

wherein a gate of the second insulated gate transistor is electrically connected to a first terminal of the seventh insulated gate transistor and a first terminal of the eighth insulated gate transistor; and

a second terminal of the second insulated gate transistor is electrically connected to a first terminal of the third insulated gate transistor, a first terminal of the fourth insulated gate transistor, and a gate of the sixth insulated gate transistor,

wherein a gate of the third insulated gate transistor is electrically connected to the first wiring, and a second terminal of the third insulated gate transistor is electrically connected to the second wiring,

wherein a gate of the fourth insulated gate transistor is electrically connected to a first terminal of the fifth insulated gate transistor, a first terminal of the sixth insulated gate transistor, a first electrode of the capacitor, a gate of the eighth insulated gate transistor, and a gate of the ninth insulated gate transistor; and

a second terminal of the fourth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the fifth insulated gate transistor is electrically connected to the first wiring, and a second terminal of the fifth insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the sixth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the seventh insulated gate transistor is electrically connected to the first wiring, and a second terminal of the seventh insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the eighth insulated gate transistor is electrically connected to the third wiring,

wherein a first terminal of the ninth insulated gate transistor is electrically connected to an output terminal, and a second terminal of the ninth insulated gate transistor is electrically connected to the fourth wiring, and

wherein a second electrode of the capacitor is electrically connected to the third wiring.

2. The semiconductor device according to claim 1, further comprising a resistor,

wherein a first terminal of the resistor is electrically connected to the gate of the first insulated gate transistor, and a second terminal of the resistor is electrically connected to the third wiring.

3. The semiconductor device according to claim 1, wherein the first high power supply potential and the second high power supply potential are the same potential.

4. A semiconductor device comprising:

first to ninth insulated gate transistors;

a capacitor;

a first wiring to which a first high power supply potential is supplied;

a second wiring to which a second high power supply potential is supplied;

a third wiring to which a first low power supply potential is supplied; and

a fourth wiring to which a second low power supply potential is supplied,

wherein a gate of the first insulated gate transistor is electrically connected to an input terminal, a first terminal of the first insulated gate transistor is electrically connected to the third wiring, and a second terminal of the first insulated gate transistor is electrically connected to a first terminal of the second insulated gate transistor,

wherein a gate of the second insulated gate transistor is electrically connected to a first terminal of the seventh insulated gate transistor and a first terminal of the eighth insulated gate transistor; and

a second terminal of the second insulated gate transistor is electrically connected to a first terminal of the third insulated gate transistor, a first terminal of the fourth insulated gate transistor, and a gate of the sixth insulated gate transistor,

wherein a gate of the third insulated gate transistor is electrically connected to the first wiring, and a second terminal of the third insulated gate transistor is electrically connected to the second wiring,

wherein a gate of the fourth insulated gate transistor is electrically connected to a first terminal of the fifth insulated gate transistor, a first terminal of the sixth insulated gate transistor, a first electrode of the capacitor, a gate of the eighth insulated gate transistor, and a gate of the ninth insulated gate transistor; and

a second terminal of the fourth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the fifth insulated gate transistor is electrically connected to the first wiring, and a second terminal of the fifth insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the sixth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the seventh insulated gate transistor is electrically connected to the first wiring, and a second terminal of the seventh insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the eighth insulated gate transistor is electrically connected to the third wiring,

wherein a first terminal of the ninth insulated gate transistor is electrically connected to an output terminal, and a second terminal of the ninth insulated gate transistor is electrically connected to the fourth wiring,

wherein a second electrode of the capacitor is electrically connected to the third wiring, and

wherein the first to ninth insulated gate transistors each have a semiconductor layer formed using an oxide semiconductor.

5. The semiconductor device according to claim 4, further comprising a resistor,

wherein a first terminal of the resistor is electrically connected to the gate of the first insulated gate transistor, and a second terminal of the resistor is electrically connected to the third wiring.

6. The semiconductor device according to claim 4, wherein a concentration of hydrogen in the oxide semiconductor detected by secondary ion mass spectrometry is 1×

10¹⁶/cm³ or less.

7. The semiconductor device according to claim 4, wherein a carrier concentration of the oxide semiconductor is less than 1×

10¹⁴/cm³.

8. The semiconductor device according to claim 4, wherein the first high power supply potential and the second high power supply potential are the same potential.

9. A semiconductor device comprising:

first to ninth insulated gate transistors;

a capacitor;

a buffer circuit;

a first wiring to which a first high power supply potential is supplied;

a second wiring to which a second high power supply potential is supplied;

a third wiring to which a first low power supply potential is supplied; and

a fourth wiring to which a second low power supply potential is supplied,

wherein a gate of the first insulated gate transistor is electrically connected to an input terminal, a first terminal of the first insulated gate transistor is electrically connected to the third wiring, and a second terminal of the first insulated gate transistor is electrically connected to a first terminal of the second insulated gate transistor,

wherein a gate of the second insulated gate transistor is electrically connected to a first terminal of the seventh insulated gate transistor and a first terminal of the eighth insulated gate transistor; and

a second terminal of the second insulated gate transistor is electrically connected to a first terminal of the third insulated gate transistor, a first terminal of the fourth insulated gate transistor, and a gate of the sixth insulated gate transistor,

wherein a gate of the third insulated gate transistor is electrically connected to the first wiring, and a second terminal of the third insulated gate transistor is electrically connected to the second wiring,

wherein a gate of the fourth insulated gate transistor is electrically connected to a first terminal of the fifth insulated gate transistor, a first terminal of the sixth insulated gate transistor, a first electrode of the capacitor, a gate of the eighth insulated gate transistor, and a gate of the ninth insulated gate transistor; and

a second terminal of the fourth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the fifth insulated gate transistor is electrically connected to the first wiring, and a second terminal of the fifth insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the sixth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the seventh insulated gate transistor is electrically connected to the first wiring, and a second terminal of the seventh insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the eighth insulated gate transistor is electrically connected to the third wiring,

wherein a first terminal of the ninth insulated gate transistor is electrically connected to an output terminal, and a second terminal of the ninth insulated gate transistor is electrically connected to the fourth wiring,

wherein a second electrode of the capacitor is electrically connected to the third wiring,

wherein the first to ninth insulated gate transistors each have a semiconductor layer formed using an oxide semiconductor, and

wherein a potential of a node at which the gate of the fourth insulated gate transistor, the first terminal of the fifth insulated gate transistor, the first terminal of the sixth insulated gate transistor, the first electrode of the capacitor, and the gate of the eighth insulated gate transistor are electrically connected is supplied to the gate of the ninth insulated gate transistor through the buffer circuit.

10. The semiconductor device according to claim 9, further comprising a resistor,

wherein a first terminal of the resistor is electrically connected to the gate of the first insulated gate transistor, and a second terminal of the resistor is electrically connected to the third wiring.

11. The semiconductor device according to claim 9, wherein a concentration of hydrogen in the oxide semiconductor detected by secondary ion mass spectrometry is 1×

10¹⁶/cm³ or less.

12. The semiconductor device according to claim 9, wherein a carrier concentration of the oxide semiconductor is less than 1×

10¹⁴/cm³.

13. The semiconductor device according to claim 9, wherein the first high power supply potential and the second high power supply potential are the same potential.

14. The semiconductor device according to claim 9,

wherein the buffer circuit includes tenth to thirteenth insulated gate transistors,

wherein a gate of the tenth insulated gate transistor is electrically connected to the first wiring, a first terminal of the tenth insulated gate transistor is electrically connected to the second wiring, and a second terminal of the tenth insulated gate transistor is electrically connected to a first terminal of the eleventh insulated gate transistor and a gate of the thirteenth insulated gate transistor,

wherein a gate of the eleventh insulated gate transistor is electrically connected to the gate of the fourth insulated gate transistor, the first terminal of the fifth insulated gate transistor, the first terminal of the sixth insulated gate transistor, the first electrode of the capacitor, and the gate of the eighth insulated gate transistor;

and a second terminal of the eleventh insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the twelfth insulated gate transistor is electrically connected to the first wiring, a first terminal of the twelfth insulated gate transistor is electrically connected to the second wiring, and a second terminal of the twelfth insulated gate transistor is electrically connected to a first terminal of the thirteenth insulated gate transistor and the gate of the ninth insulated gate transistor, and

wherein a second terminal of the thirteenth insulated gate transistor is electrically connected to the third wiring.

15. The semiconductor device according to claim 9,

wherein the buffer circuit includes tenth to thirteenth insulated gate transistors,

wherein a gate of the tenth insulated gate transistor is electrically connected to the gate of the second insulated gate transistor, the first terminal of the seventh insulated gate transistor, and the first terminal of the eighth insulated gate transistor;

a first terminal of the tenth insulated gate transistor is electrically connected to the second wiring; and

a second terminal of the tenth insulated gate transistor is electrically connected to a first terminal of the eleventh insulated gate transistor and a gate of the thirteenth insulated gate transistor,

wherein a gate of the eleventh insulated gate transistor is electrically connected to the gate of the fourth insulated gate transistor, the first terminal of the fifth insulated gate transistor, the first terminal of the sixth insulated gate transistor, the first electrode of the capacitor, the gate of the eighth insulated gate transistor, and a gate of the twelfth insulated gate transistor; and

a second terminal of the eleventh insulated gate transistor is electrically connected to the third wiring,

wherein a first terminal of the twelfth insulated gate transistor is electrically connected to the second wiring, and a second terminal of the twelfth insulated gate transistor is electrically connected to a first terminal of the thirteenth insulated gate transistor and the gate of the ninth insulated gate transistor, and

wherein a second terminal of the thirteenth insulated gate transistor is electrically connected to the third wiring.