SELF-POWERED EVENT DETECTION DEVICE

• US 20110115548A1
• Filed: 11/12/2010
• Published: 05/19/2011
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Original Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Inventors: Roz, Thierry, Marinelli, Filippo, Kamp, David A.
• Granted Patent: US 8,422,293 B2
• Time in Patent Office: Days
• US Class Current: 327/530
• CPC Class Codes: E05B 2047/0058 by batteries
• CPC Class Codes: E05B 2047/0062 by generator
• CPC Class Codes: E05B 2047/0064 by solar cells
• CPC Class Codes: E05B 39/00 Locks giving indication of authorised or unauthorised unlocking with key identification means E05B35/001; alarm locks E05B45/00
• CPC Class Codes: E05B 45/06 Electric alarm locks E05B45/005 takes precedence
• CPC Class Codes: E05B 51/023 actuated in response to external pressure, blast or explosion E05B65/102 takes precedence
• CPC Class Codes: E05B 67/22 Padlocks with sliding shackles, with or without rotary or pivotal movement
• CPC Class Codes: G08B 13/06 by tampering with fastening
• CPC Class Codes: G08B 29/181 due to failing power supply

Abstract

The self-powered detection device comprises at least a non-volatile memory cell (24) and a sensor (16) which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, the memory cell being arranged for storing, by using the electrical power of said electrical stimulus pulse, at least a bit of information relative to the detection by the sensor of at least a first physical or chemical action or phenomenon applied to it with at least a given strength or intensity. The non-volatile memory cell is formed by a FET transistor (T1) having a control gate, a first diffusion (DRN) defining a first input and a second diffusion (SRC) defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode of this self-powered detection device, it receives on a set terminal, among said control gate and said first and second inputs, a voltage stimulus signal resulting from the first physical or chemical action or phenomenon. In a first embodiment of the invention, the set terminal of the FET transistor is its control gate and the first input of this FET transistor is connected to the ground of the sensor in said detection mode. In a further embodiment of the invention, the set terminal of the FET transistor is its first input and the control gate of this FET transistor is connected to the ground (GND) of the sensor in the detection mode.

Claims

1. A self-powered detection device comprising at least a non-volatile memory cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said memory cell being arranged for storing, by using the electrical power of said electrical stimulus pulse, at least a bit of information relative to the detection by said sensor of at least a first physical or chemical action or phenomenon applied to it with at least a given strength or intensity, wherein said non-volatile memory cell is formed by a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input, and wherein this FET transistor is set to its written logical state from its initial logical state when, in a detection mode of this self-powered detection device, it receives on a set terminal, among said control gate and said first and second inputs, a voltage stimulus signal resulting from said first physical or chemical action or phenomenon.

2. The self-powered detection device according to claim 1, wherein said set terminal is the control gate of said FET transistor, and wherein said first input of this FET transistor is connected to the ground of the sensor in said detection mode.

3. The self-powered detection device according to claim 1, wherein said set terminal is said first input of said FET transistor, and wherein said control gate of this FET transistor is connected to the ground of the sensor in said detection mode.

4. The self-powered detection device according to claim 2, wherein said FET transistor is of the ‘

floating gate’

type with a tunnel oxide over the drain diffusion, and wherein said first input of this FET transistor is its drain.

5. The self-powered detection device according to claim 3, wherein said FET transistor is of the ‘

floating gate’

type with a tunnel oxide over the drain diffusion, and wherein said first input of this FET transistor is its drain.

6. The self-powered detection device according to claim 2, wherein said FET transistor is of the ‘

floating gate’

type with a tunnel oxide over the channel zone or of the SONOS type, and wherein said first input of this FET transistor is its drain or its source.

7. The self-powered detection device according to claim 3, wherein said FET transistor is of the ‘

floating gate’

type with a tunnel oxide over the channel zone or of the SONOS type, and wherein said first input of this FET transistor is its drain or its source.

8. The self-powered detection device according to claim 1, wherein it comprises reading means of said non-volatile memory cell or is arranged to be coupled to such reading means which are active when powered by a power source, these reading means being, in a read mode, electrically connected to the first input or the second input of said FET transistor and arranged to detect the state of this non-volatile memory cell by sensing the level of an electrical current flowing through this first or second input.

9. The self-powered detection device according to claim 2, wherein it comprises reading means of said non-volatile memory cell or is arranged to be coupled to such reading means which are active when powered by a power source, these reading means being, in a read mode, electrically connected to the first input or the second input of said FET transistor and arranged to detect the state of this non-volatile memory cell by sensing the level of an electrical current flowing through this first or second input.

10. The self-powered detection device according to claim 3, wherein it comprises reading means of said non-volatile memory cell or is arranged to be coupled to such reading means which are active when powered by a power source, these reading means being, in a read mode, electrically connected to the first input or the second input of said FET transistor and arranged to detect the state of this non-volatile memory cell by sensing the level of an electrical current flowing through this first or second input.

11. The self-powered detection device according to claim 8, wherein said reading means is formed by a latch providing at its output a logical signal relative to the state of said FET transistor.

12. The self-powered detection device according to claim 9, wherein said reading means is formed by a latch providing at its output a logical signal relative to the state of said FET transistor.

13. The self-powered detection device according to claim 10, wherein said reading means is formed by a latch providing at its output a logical signal relative to the state of said FET transistor.

14. The self-powered detection device according to claim 4, wherein it further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, these reset means being, in a reset mode, arranged to reset the FET transistor by applying a voltage signal of inversed polarity, relatively to said voltage stimulus signal, between said control gate and said first input of this FET transistor.

15. The self-powered detection device according to claim 5, wherein it further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, these reset means being, in a reset mode, arranged to reset the FET transistor by applying a voltage signal of inversed polarity, relatively to said voltage stimulus signal, between said control gate and said first input of this FET transistor.

16. The self-powered detection device according to claim 6, wherein it further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, these reset means being, in a reset mode, arranged to reset the FET transistor by applying a voltage signal of inversed polarity, relatively to said voltage stimulus signal, between said control gate and said first input or said second input of this FET transistor.

17. The self-powered detection device according to claim 7, wherein it further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, these reset means being, in a reset mode, arranged to reset the FET transistor by applying a voltage signal of inversed polarity, relatively to said voltage stimulus signal, between said control gate and said first input or said second input of this FET transistor.

18. The self-powered detection device according to claim 14, wherein said reset means comprises a control circuit and a level shifter controlled by this control circuit.

19. The self-powered detection device according to claim 15, wherein said reset means comprises a control circuit and a level shifter controlled by this control circuit.

20. The self-powered detection device according to claim 16, wherein said reset means comprises a control circuit and a level shifter controlled by this control circuit.

21. The self-powered detection device according to claim 17, wherein said reset means comprises a control circuit and a level shifter controlled by this control circuit.

22. The self-powered detection device according to claim 8, wherein an isolation circuit is provided between said FET transistor and said reading means, this isolation circuit being arranged for isolating this FET transistor from this reading means in said detection mode but for connecting it in said read mode.

23. The self-powered detection device according to claim 9, wherein an isolation circuit is provided between said FET transistor and said reading means, this isolation circuit being arranged for isolating this FET transistor from this reading means in said detection mode but for connecting it in said read mode.

24. The self-powered detection device according to claim 10, wherein an isolation circuit is provided between said FET transistor and said reading means, this isolation circuit being arranged for isolating this FET transistor from this reading means in said detection mode but for connecting it in said read mode.

25. The self-powered detection device according to claim 2, wherein it further comprises a switch arranged between the ground of the sensor and said first input of said FET transistor, and wherein this switch has its control gate connected to the control gate of this FET transistor so that it is turned on when a voltage stimulus signal is provided to this control gate of this FET transistor thereby connecting its first input to ground.

26. The self-powered detection device according to claim 3, wherein it further comprises a switch arranged between the ground of the sensor and said control gate of said FET transistor, and wherein this switch has its control gate connected to the set terminal of this FET transistor so that it is turned on when a voltage stimulus signal is provided to this set terminal of this FET transistor thereby connecting its control gate to ground.

27. The self-powered detection device according to claim 25, wherein said switch is formed by a second FET transistor which control gate is connected to said set terminal of said FET transistor.

28. The self-powered detection device according to claim 26, wherein said switch is formed by a second FET transistor which control gate is connected to said set terminal of said FET transistor.

29. The self-powered detection device according to claim 1, wherein said non-volatile memory cell can be reset, and wherein the self-powered detection device further comprises an OTP memory a bit of which is automatically set when this electronic unit is powered and said non-volatile memory cell has been set to its written state.

30. The self-powered detection device according to claim 29, wherein said OTP memory comprises several Bits which are successively set each time the non-volatile memory cell is set after a reset action.