SWITCHING CONTROLLER HAVING SWITCHING FREQUENCY HOPPING FOR POWER CONVERTER

• US 20110116287A1
• Filed: 01/25/2011
• Published: 05/19/2011
• Est. Priority Date: 08/05/2008
• Status: Abandoned Application

• Current Assignee: Fairchild Corporation (ON Semiconductor Corporation)
• Original Assignee: System General Corporation (ON Semiconductor Corporation)
• Inventors: Yang, Ta-Yung, Huang, Wei-Hsuan, Lin, Jenn-Yu G.
• Application Number:
  US13/012,800
• Publication Number:
  US 20110116287A1
• Time in Patent Office: Days
• US Class Current: 363/21.13
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

A switching controller having switching frequency hopping for a power converter includes an oscillator generating a pulse signal for determining a switching frequency of a switching signal, a maximum duty-cycle circuit generating a maximum duty-cycle signal in response to the switching signal for determining the switching frequency of the switching signal, a pattern generator generating a digital pattern code in response to a clock signal, a programmable capacitor coupled to the pattern generator and the oscillator for modulating the switching frequency of the switching signal in response to the digital pattern code, and a PWM circuit coupled to the oscillator and the maximum duty-cycle circuit for generating the switching signal in accordance with the pulse signal and the maximum duty-cycle signal. A maximum on-time of the switching signal is limited by the maximum duty-cycle signal. The switching signal is utilized to switch a transformer of the power converter.

Claims

1. A switching controller having switching frequency hopping for a power converter, comprising:

a first oscillator, generating a pulse signal for determining a switching frequency of a switching signal;

a maximum duty-cycle circuit, generating a maximum duty-cycle signal in response to the switching signal for determining the switching frequency of the switching signal;

a pattern generator with a second oscillator, generating a digital pattern code in response to a clock signal, wherein the clock signal is generated by the second oscillator;

a programmable capacitor, coupled to the pattern generator and the first oscillator for modulating the switching frequency of the switching signal in response to the digital pattern code; and

a PWM circuit, coupled to the first oscillator and the maximum duty-cycle circuit for generating the switching signal in accordance with the pulse signal and the maximum duty-cycle signal, a maximum on-time of the switching signal being limited by the maximum duty-cycle signal, wherein the switching signal is utilized to switch a transformer of the power converter.

2. The switching controller as claimed in claim 1, wherein a switching period of the pulse signal is correlated to a switching period of the switching signal.

3. The switching controller as claimed in claim 1, wherein a switching period generated by the first oscillator is independent of a switching period generated by the second oscillator.

4. The switching controller as claimed in claim 1, wherein a switching period of the pulse signal is independent of a switching period of the clock signal.

5. The switching controller as claimed in claim 1, wherein the digital pattern code controls switching-capacitor sets to connect a saw-tooth capacitor in parallel for modulating an oscillation signal, and different capacitances of the saw-tooth capacitor cycle-by-cycle generates frequency variation of the switching signal.

6. The switching controller as claimed in claim 1, wherein the programmable capacitor comprises a plurality of switching-capacitor sets connected to one another in parallel, the switching-capacitor sets are formed by several switches and capacitors connected in series respectively, and the switches are controlled by the digital pattern code.

7. The switching controller as claimed in claim 1, wherein the second oscillator comprises:

a first switch, coupled to a first charging current, the first switch being controlled by the clock signal;

a first capacitor, coupled to the first charging current and connected to the first switch in parallel, wherein the first capacitor is charged by the first charging current once the first switch is turned off, and the first capacitor is discharged when the first switch is turned on; and

a trigger and a first inverter, coupled to the first switch, the first charging current, and the first capacitor for generating the clock signal.

8. The switching controller as claimed in claim 1, wherein the maximum duty-cycle circuit comprises:

a comparator, coupled to the PWM circuit for outputting the maximum duty-cycle signal, and a first input of the comparator coupled to a reference voltage; and

a second capacitor, coupled to a second input of the comparator, wherein the comparator outputs the maximum duty-cycle signal with a low level once a storage voltage of the second capacitor is higher than the reference voltage, and the comparator outputs the maximum duty-cycle signal with a high level when the storage voltage of the second capacitor is lower than the reference voltage.

9. The switching controller as claimed in claim 8, wherein the maximum duty-cycle circuit further comprises:

a second charging current, coupled to the second capacitor for charging the second capacitor;

a second switch, coupled to the second charging current, the second switch being controlled by the switching signal, wherein the second capacitor is charged by the second charging current once the second switch is turned on;

arid

a third switch, coupled to the second switch and connected to the second capacitor in parallel, the third switch being controlled by an inverse switching signal, wherein the second capacitor is discharged when the third switch is turned on.

10. The switching controller as claimed in claim 9, wherein the maximum duty-cycle circuit further comprises:

a second inverter, coupled to a control input of the third switch for inverting the switching signal and accordingly outputting the inverse switching signal to control the third switch.