Refresh Circuitry for Phase Change Memory
First Claim
1. A memory device comprising:
- an array of memory cells;
sense circuitry to read a current data set from a plurality of the memory cells of the array of memory cells; and
control circuitry to perform a refresh operation on the array of memory cells if there is a difference between the current data set read by the sense circuitry and an expected data set.
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Abstract
A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.
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Citations
23 Claims
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1. A memory device comprising:
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an array of memory cells; sense circuitry to read a current data set from a plurality of the memory cells of the array of memory cells; and control circuitry to perform a refresh operation on the array of memory cells if there is a difference between the current data set read by the sense circuitry and an expected data set. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for operating a memory device comprising an array of memory cells, the method comprising:
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reading the array of memory cells; determining a difference between a current data set from a plurality of the memory cells of the array of memory cells and an expected data set; and upon determination of the difference, performing a refresh operation on the array of memory cells. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification