MEMORY DEVICE WITH TEST MECHANISM

• US 20110116332A1
• Filed: 11/16/2009
• Published: 05/19/2011
• Est. Priority Date: 11/16/2009
• Status: Active Grant

• Current Assignee: NSCore, Inc.
• Original Assignee: NSCore, Inc.
• Inventors: Sakata, Hajime, NAKA, TOMOMI
• Granted Patent: US 8,213,247 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes a plurality of reference cell transistors employed to successively produce varying amounts of currents, a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents, and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cell transistors arranged in a matrix and each configured to store data; and

a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors,

wherein the test circuit includes;

a plurality of reference cell transistors employed to successively produce varying amounts of currents;

a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents; and

a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal.

2. The semiconductor memory device as claimed in claim 1, wherein the memory cell transistors are MIS transistors configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change.

3. The semiconductor memory device as claimed in claim 1, wherein the reference cell transistors are each configured to produce an identical amount of current, and one or more selected ones of the reference cell transistors are concurrently made conductive to produce a desired amount of current.

4. The semiconductor memory device as claimed in claim 1, wherein the reference cell transistors are configured to produce varying amounts of respective currents, and a selected one of the reference cell transistors is made conductive to produce a desired amount of current.

5. The nonvolatile semiconductor memory device as claimed in claim 1, wherein one of the varying amounts of currents is a maximum tolerable current amount that is allowed to flow through any one of the memory cell transistors.

6. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the code generating circuit is configured to generate the code such that the code has a value indicative of one of the varying amounts of currents that is detected as a smallest to exceed the amount of test current.

7. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the varying amounts of currents are arranged in descending order or ascending order, and the code generating circuit is configured to generate the code such that the code has a value corresponding to a sequence number of one of the varying amounts of currents as defined by said order, said one of the varying amounts of currents being detected as a smallest to exceed the amount of test current.

8. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the code generating circuit is configured to generate the code such that the code has a value indicative of one of the varying amounts of currents that is detected as a largest to fall below the amount of test current.

9. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the varying amounts of currents are arranged in descending order or ascending order, and the code generating circuit is configured to generate the code such that the code has a value corresponding to a sequence number of one of the varying amounts of currents as defined by said order, said one of the varying amounts of currents being a largest to fall below the amount of test current.

10. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the test circuit is configured to output the output signal simultaneously with respect to both a first one of the memory cell transistors and a second one of the memory cell transistors, and the plurality of reference cell transistors are used in common for comparison with the amount of test current flowing through the first one of the memory cell transistors and for comparison with the amount of test current flowing through the second one of the memory cell transistors.

11. The nonvolatile semiconductor memory device as claimed in claim 10, wherein the first one of the memory cell transistors and the second one of the memory cell transistors are a pair of memory cell transistors whose cell currents are compared with each other to determine a value of the stored data.