BALANCING WORKLOAD IN A MULTIPROCESSOR SYSTEM RESPONSIVE TO PROGRAMMABLE ADJUSTMENTS IN A SYNCRONIZATION INSTRUCTION

• US 20110119469A1
• Filed: 06/08/2010
• Published: 05/19/2011
• Est. Priority Date: 11/13/2009
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ohmacht, Martin
• Application Number:
  US12/796,389
• Publication Number:
  US 20110119469A1
• Time in Patent Office: Days
• US Class Current: 712/216
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

In a multiprocessor system with threads running in parallel, workload balancing is facilitated by recognizing a plurality of levels of sub-tasks of a memory synchronization instruction and selectively choosing for at least one thread to do less than all of levels of these sub-tasks in response to the memory synchronization instruction. Which thread waits to synchronize can be impacted by this choice. The programmer can cause a thread expected to be a bottleneck to wait less than other threads. Where one thread is a producer and another thread is a consumer, types of memory synchronization can be adapted to these roles.

Claims

1. A computer method comprising carrying out operations in a multiprocessor system, the operations comprising:

processing a plurality of software threads in parallel;

responsive to a first thread, decoding a first memory synchronization instruction, the first instruction corresponding to a first synchronization level;

responsive to the first synchronization level, implementing a first partial synchronization task;

responsive to a second thread, decoding a second memory synchronization instruction, the second instruction corresponding to a second synchronization level different from, but compatible with, the first synchronization level;

responsive to the second thread, implementing a second partial synchronization task responsive to the second synchronization level, the second partial synchronization task being complementary with the first partial synchronization task, so that the first and second synchronization tasks cooperate to achieve full synchronization.

2. The method of claim 1, wherein the first and second levels are chosen to reduce waiting time for one of the first and second threads, while increasing wait time for the other of the first and second threads.

3. The method of claim 2, wherein

the first thread writes data;

the second thread reads the data;

the first synchronization level causes a generation change within the system related to the write; and

the second synchronization level causes the second thread to wait for the generation change to complete.

4. The method of claim 3, wherein the central generation indication is derived responsive to a generation counter.

5. The method of claim 3, wherein the central generation indication is derived responsive to a reclaim pointer.

6. The method of claim 1, wherein the first and second instructions are memory synchronization instructions in accordance with a given instruction architecture modified by parameters conveyed in accordance with memory-mapped i/o.

7. The method of claim 1, wherein the first thread is a producer thread and the second thread is a consumer thread and the method comprises:

in the producer thread, requesting to write data;

in the producer thread, requesting a generation increment;

in the producer thread, waiting for the generation increment, without any other data ready indication;

in the producer thread, setting a data ready flag;

in the consumer thread, waiting for the data ready flag;

in the consumer thread, waiting for a value in a reclaim pointer to reach a desired generation; and

in the consumer thread, using the data responsive to the data ready flag and the reclaim pointer value.

8. A multiprocessor system comprising:

facilities adapted to run a plurality of threads in parallel;

a central generation indication module adapted to associate generations with memory synchronization instructions; and

facilities adapted to decode at least one memory synchronization instruction in at least one of the threads, in accordance with a memory synchronization protocol that implements a plurality of levels of memory synchronization each level having a respective distinct mode of operation responsive to the central generation indication module.

9. The system of claim 8, wherein each level is invoked responsive to respective parameters communicable in association with the memory synchronization instruction.

10. The system of claim 8, comprising a plurality of generation detectors, each adapted to detect a generation associated with a respective type of instruction, such that each level of memory synchronization instruction is associated with a respective distinctive use of the generation detectors.

11. The system of claim 10, wherein each thread is a associated with three generation detectors,

a first detector detecting a generation of a last store;

a second detector detecting a generation of a last load or store; and

a third detector detecting a generation of a last memory synchronization instruction.

12. The system of claim 11, wherein each detector has an associated flag indicating whether a respective generation of an instruction detected by that detector has completed.

13. The system of claim 11, wherein

the third detector is primed with the current generation;

the memory synchronization instruction is a full sync that completes when the third detector indicates completion; and

until completion, the memory synchronization instruction requests a generation change to one more than the generation detected by the third detector.

14. The system of claim 11, wherein

the memory synchronization instruction is a non-cumulative barrier that completes when the second detector indicates completion;

and

until completion, the memory synchronization instruction requests a generation change to one more than the generation detected by the second detector.

15. The system of claim 11, wherein

the memory synchronization instruction is a producer sync that completes when the first detector indicates completion;

and

until completion, the memory synchronization instruction requests a generation change to one more than the generation detected by the first detector.

16. The system of claim 11, wherein

the memory synchronization instruction is a generation change sync that completes if either

the second detector indicates completion or

if the generation stored in the second detector differs from a central generation indication;

and

the system is adapted such that, if the memory synchronization instruction does not complete immediately, a generation change is requested for one more than the generation stored in the second detector.

17. The system of claim 11, wherein

the memory synchronization instruction is a producer generation change sync that completes if

the first detector indicates completion;

or

the generation detected by the first detector is different from a central generation indication; and

the system is adapted such that, if the memory synchronization instruction does not complete immediately, a generation change is requested for one more than the generation detected by the first detector.

18. The system of claim 11, wherein

the third detector is primed with the current generation minus one;

the memory synchronization instruction is a consumer sync that completes if the third detector indicates completion; and

the system is adapted such that, until completion, a generation change is requested for one more than the generation detected by the third detector.

19. A computer method comprising carrying out operations in a multiprocessor system, the operations comprising

responsive to a given thread running on the system, recognizing a memory synchronization instruction, the instruction implicating a plurality of memory synchronization sub-tasks;

responsive to the instruction, invoking at least one memory synchronization facility in accordance with a synchronization scheme including a plurality of synchronization levels; and

distributing the sub-tasks responsive to the levels so as to offload sub-tasks from or allocate subtasks to the given thread.

20. The method of claim 19, wherein at least one of the sub-tasks comprises requesting a change of generation with respect to a central generation indication of the system.

21. The method of claim 19, wherein at least one of the sub-tasks comprises checking at least one generation detector associated with the given thread and indicating completion responsive to such checking.

22. The method of claim 19, wherein the given thread is one of a group of threads working together and one of the group is considered a bottleneck, so the distributing offloads sub-tasks from the bottleneck.

25. The product of claim 22, wherein at least one of the sub-tasks comprises monitoring completion of a generation associated with a particular type of instruction associated with a respective level of respective memory synchronization instruction.

23. A computer program product for carrying out tasks within a multiprocessor system, the computer program product comprising. a storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing a method comprising:

implementing the tasks in accordance with a plurality of threads adapted to run in parallel;

specifying first and second memory synchronization instructions in accordance with a memory synchronization protocol that implicates a plurality of memory synchronization sub-tasks, respective sub-sets of the sub-tasks corresponding to respective levels of synchronization, wherein the first and second memory synchronization instructions are adapted to offload given sub-tasks from a thread expected to be a bottleneck to a thread expected not to be a bottleneck.

24. The product of claim 23, wherein at least one of the sub-tasks comprises requesting a generation change from a central generation indication device between a memory access request and a guard location in at least one of the threads.

24-1. (canceled)