GENERATION-BASED MEMORY SYNCHRONIZATION IN A MULTIPROCESSOR SYSTEM WITH WEAKLY CONSISTENT MEMORY ACCESSES

• US 20110119470A1
• Filed: 06/08/2010
• Published: 05/19/2011
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ohmacht, Martin
• Granted Patent: US 8,832,403 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Claims

1. A multiprocessor system adapted to carry out parallel threads of instructions and comprising

a plurality of units for issuing and/or queuing memory access requests;

and

a central synchronization controller adapted to communicate synchronization control information to and/or from the units via point to point communication rather than via a bus.

2. The system of claim 1, wherein

the units queuing memory requests comprise a plurality of prefetch units and a plurality of data caches;

and

the system comprises facilities adapted to receive information regarding the memory requests being queued in order to support generation completion detection.

3. A multiprocessor system adapted to carry out parallel threads of instructions and comprising:

a plurality of units for issuing and/or queuing memory access requests; and

a central synchronization controller adapted to supply a generation tag to the memory access requests.

4. The system of claim 3, wherein

the system comprises a plurality of processors for carrying out the threads, and at least one of the threads includes a memory synchronization instruction;

and

the central synchronization controller is adapted to increment a central generation counter responsive to the memory synchronization instruction.

5. The system of claim 3, wherein the central generation controller comprises a wrapping generation counter and a wrapping reclaim pointer that cannot pass each other.

6. The system of claim 5, wherein generation completion is detected responsive to the reclaim pointer.

7. The system of claim 3, wherein the units comprise a plurality of processing cores, a plurality of prefetch units, and a plurality of data caches.

8. The system of claim 3,

wherein the units queuing memory access requests comprise one or more of:

at least one supplementary processing and/or prefetch unit;

at least one L2 cache;

at least one direct memory access unit; and

at least one peripheral component interconnect express unit; and

the system comprises facilities adapted to receive information regarding the memory requests being queued in order to support generation completion detection.

9. The system of claim 8, wherein each unit queuing memory access requests is adapted to produce an indication of generations of memory accesses in flight within that unit.

10. The system of claim 9, wherein the indication is a vector with a bit for each generation.

11. The system of claim 10, wherein the facilities comprise an OR reduce tree coupled to receive and combine the vectors from the units queuing memory access requests to yield a global indication of generations of memory accesses in flight.

12. The system of claim 11, comprising a plurality of interface units adapted to

receive and process at least one output responsive to the tree;

and

treat a memory access request as completed responsive to the output indicating that a tagging result associated with the request is no longer in flight in the system.

13. The system of claim 3,

comprising a plurality of processors adapted to issue memory synchronization instructions and

wherein system is adapted to tag concurrent memory access requests with a same generation number, responsive to the synchronization controller.

14. The system of claim 3, wherein

the synchronization controller comprises

a generation counter;

a reclaim pointer and; and

a broadcast facility for broadcasting values of the generation counter and the reclaim pointer to at least some of the units; and

at least one of the units comprises an interface unit adapted to request a new generation responsive to the memory synchronization instruction; and

the generation controller is adapted to increment the generation counter responsive to the interface unit and relative positions of the reclaim pointer and generation counter.

15. The system of claim 3, comprising

a plurality of processors adapted to issue memory synchronization requests;

and

a plurality of detectors, coupled with the processors, adapted to;

detect generations of instructions issued by the processors; and

record whether generations associated with the instructions are completed

16. The system of claim 15, comprising an interface unit that includes the detectors, the interface unit being adapted to

aggregate concurrent synchronization requests from a plurality of threads requesting a new generation;

receive a common generation indication for the concurrent synchronization requests; and

and notify threads of generation completion.

17. A method for memory synchronization for use in a multiprocessor system, the method comprising carrying out operations in at least one data processing device, the operations comprising:

broadcasting a central generation indication from a memory synchronization unit; and

delaying memory access requests responsive to values of the central generation indication.

18. The method of claim 17, wherein the operations comprise

tagging memory access requests responsive to the central access indication;

OR-ing bits from results of tagging to determine what generations are in flight; and

supplying a value responsive to a result of the OR-ing to a unit requesting memory synchronization.

19. The method of claim 17, wherein

the central generation indication comprises a pointer value and

the operations comprise,

holding incrementation of the pointer value so long as a given generation is in flight;

and

when given generations in flight are completed, incrementing the pointer value.

20. The method of claim 17, wherein the central indication comprises a first count indicating a generation and a second count indicating a reclaim pointer.

21. The method of claim 20, comprising preventing the first and second count from passing each other.

22. A central memory synchronization module for use in a multiprocessor system, the system comprising a plurality of processors, the module comprising

at least one global generation unit for storing a global numeric generation indication;

at least one global or-reduce tree, for aggregating information about current generations of memory requests in flight; and

at least one broadcast facility for broadcasting the generation indication and a result derived from the tree.

23. The module of claim 22,

wherein the global generation unit comprises:

a counter for defining a current generation of memory access; and

a reclaim pointer for pointing to an oldest generation in flight; and

further comprising;

at least one interface unit for coupling with at least one device control register bus;

at least one broadcast interface for providing a value of the counter and the reclaim pointer to the system; and

a request interface for coupling within the system and receiving synchronization requests.

24. The module of claim 22, wherein the global OR reduce tree comprises:

means for receiving a plurality of respective vectors—

each respective vector having a respective bit for each possible generation, indicating whether there are memory accesses in flight for that generation—

from each unit capable of requesting memory access; and

at least one means for OR-ing the respective vectors to determine whether there are memory access requests in flight for any generation.

25. A system comprising

the module of claim 22 and

at least one interface unit for coupling with a synchronization requesting processor and an OR reduce end-point of the global generation unit, the interface unit including a plurality of respective generation detectors.