Multi-Core System on Chip

• US 20110119672A1
• Filed: 11/13/2009
• Published: 05/19/2011
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ramaraju, Ravindraraj, Bearden, David R., Moyer, William C.
• Granted Patent: US 8,566,836 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.

Claims

1. A method for operating a multi-core processing device, comprising:

measuring a processing speed parameter for each of a plurality of cores;

storing each measured processing speed parameter for each of a plurality of cores in a storage device; and

upon identifying a processing task that can not be run by a plurality of cores, selecting a core having a fastest measured processing speed parameter to run the processing task.

2. The method of claim 1, where measuring the processing speed parameter comprises measuring a maximum operating frequency parameter for each of the plurality of cores.

3. The method of claim 1, where measuring a processing speed parameter comprises periodically measuring the processing speed parameter on a predetermined basis.

4. The method of claim 1, where measuring the processing speed parameter comprises measuring a maximum operating frequency parameter for each of the plurality of cores using a critical path monitoring circuit located at each core.

5. The method of claim 1, where storing each measured processing speed parameter comprises storing each measured processing speed parameter in a device control register.

6. The method of claim 1, where storing each measured processing speed parameter comprises tagging each core with a corresponding measured maximum operating speed parameter.

7. The method of claim 1, where an operating system selects the core having the fastest measured processing speed parameter to run the processing task.

8. The method of claim 1, where the multi-core processing device is constructed on a single integrated circuit system on a chip.

9. The method of claim 1, where measuring the processing speed parameter for each of the plurality of cores comprises:

measuring a first processing speed parameter for each of the plurality of cores operating with a first operating supply voltage; and

measuring a second processing speed parameter for each of the plurality of cores operating with a second operating supply voltage that is different from the first operating supply voltage.

10. A multi-core system on chip (SOC), comprising:

a plurality of cores, each core comprising a performance measurement circuit for measuring a performance parameter value for said core; and

at least a first storage device for storing the performance parameter values for the plurality of cores for use in selecting a core having maximized or minimized performance parameter value to run a processing task that can not be run by the plurality of cores.

11. The multi-core SOC of claim 10, where the performance measurement circuit at each core comprises a critical path monitoring (CPM) circuit.

12. The multi-core SOC of claim 10, where the first storage device comprises a device control registry located at a first core.

13. The multi-core SOC of claim 10, where the first storage device comprises a device control registry which stores a core identification value and a measured maximum operating frequency value for each core.

14. The multi-core SOC of claim 10, where the first storage device comprises a device control registry which stores, for each core, a core identification value, a measured maximum operating frequency value and a corresponding operating voltage value.

15. The multi-core SOC of claim 10, where the plurality of cores all share a common external voltage supply.

16. The multi-core SOC of claim 10, where a plurality of external voltage supplies are provided to the plurality of cores.

17. The multi-core SOC of claim 10, where each of the plurality of cores comprises a core-specific clock circuit for applying a clock multiplier value to a received clock reference signal.

18. The multi-core SOC of claim 10, where the at least a first storage device stores a maximum operating frequency value for each of the plurality of cores for use in selecting a core having the fastest maximum operating frequency value to run the processing task that can not be run by the plurality of cores.

19. The multi-core SOC of claim 10, further comprising control logic for selecting a sub-plurality of cores to run a processing task that can not be run by the plurality of cores by using the performance parameter values to identify the fastest sub-plurality of cores.

22. The method of claim 19, where storing each measured maximum processing speed value comprises storing each measured maximum processing speed value for each of the multiple cores in a device control registry along with an operating voltage value at which the maximum processing speed value is measured.

20. In a multi-core processor comprising multiple cores which are controlled by system logic, a method for executing single core applications and multi-core applications comprising:

measuring a maximum processing speed value for each of the multiple cores for at least a first operating voltage value;

storing each measured maximum processing speed value for each of the multiple cores;

running a multi-core application on a plurality of the multiple cores by controlling each of the plurality of the multiple cores to run at a speed which is identified from the stored maximum processing speed values to be the slowest maximum processing speed of the plurality of the multiple cores; and

running a single core application on a single core which is identified from the stored maximum processing speed values for the multiple cores as being the fastest core.

21. The method of claim 20, where storing each measured maximum processing speed value comprises storing each measured maximum processing speed value for each of the multiple cores in a device control registry along with an operating voltage value at which the maximum processing speed value is measured.