SEMICONDUCTOR DEVICE

• US 20110121286A1
• Filed: 11/18/2010
• Published: 05/26/2011
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,476,626 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

a signal line; and

a word line,

wherein a plurality of memory cells are connected in series between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other, and

wherein the bit line and the first drain electrode are electrically connected to each other.

2. The semiconductor device according to claim 1,

wherein the signal line and the second gate electrode are electrically connected to each other, and

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.

3. The semiconductor device according to claim 1,

wherein the signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other, and

wherein the word line, the second gate electrode, and the other electrode of the capacitor are electrically connected to one another.

4. The semiconductor device according to claim 1, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

6. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

9. The semiconductor device according to claim 1, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

10. The semiconductor device according to claim 1, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

11. A semiconductor device comprising:

a source line;

a bit line;

a signal line;

a word line;

a first selection line;

a second selection line;

a third transistor which is electrically connected to the first selection line in a third gate electrode; and

a fourth transistor which is electrically connected to the second selection line in a fourth gate electrode,

wherein a plurality of memory cells are connected in series between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer;

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line and the first drain electrode are electrically connected to each other,

wherein the bit line is electrically connected to the first drain electrode through the third transistor, and

wherein the source line is electrically connected to the first source electrode through the fourth transistor.

12. The semiconductor device according to claim 11,

wherein the signal line and the second gate electrode are electrically connected to each other;

and

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.

13. The semiconductor device according to claim 11,

wherein the signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other;

and

wherein the word line, the second gate electrode, and the other electrode of the capacitor are electrically connected to one another.

14. The semiconductor device according to claim 11, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

15. The semiconductor device according to claim 11, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

16. The semiconductor device according to claim 11, wherein the semiconductor material is silicon.

17. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

18. The semiconductor device according to claim 11, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

19. The semiconductor device according to claim 11, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

20. The semiconductor device according to claim 11, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

21. A semiconductor device comprising:

a source line;

a bit line;

a signal line; and

a word line,

wherein a plurality of memory cells are connected in series between the source line and the bit line;

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line and the first drain electrode are electrically connected to each other, and

wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions.

22. The semiconductor device according to claim 21,

wherein the signal line and the second gate electrode are electrically connected to each other;

and

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.

23. The semiconductor device according to claim 21,

wherein the signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other;

and

wherein the word line, the second gate electrode, and the other electrode of the capacitor are electrically connected to one another.

24. The semiconductor device according to claim 21, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

25. The semiconductor device according to claim 21, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

26. The semiconductor device according to claim 21, wherein the semiconductor material is silicon.

27. The semiconductor device according to claim 21, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

28. The semiconductor device according to claim 21, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

29. The semiconductor device according to claim 21, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

30. The semiconductor device according to claim 21, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

31. A semiconductor device comprising:

a source line;

a bit line;

a signal line;

a word line;

a first selection line;

a second selection line;

a third transistor which is electrically connected to the first selection line in a third gate electrode; and

a fourth transistor which is electrically connected to the second selection line in a fourth gate electrode,

wherein a plurality of memory cells are connected in series between the source line and the bit line,

wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,

wherein the first transistor is provided in a substrate containing a semiconductor material,

wherein the second transistor comprises an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line and the first drain electrode are electrically connected to each other,

wherein the bit line is electrically connected to the first drain electrode through the third transistor,

wherein the source line is electrically connected to the first source electrode through the fourth transistor, and

wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions.

32. The semiconductor device according to claim 31,

wherein the signal line and the second gate electrode are electrically connected to each other;

and

wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.

33. The semiconductor device according to claim 31,

wherein the signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other;

and

wherein the word line, the second gate electrode, and the other electrode of the capacitor are electrically connected to one another.

34. The semiconductor device according to claim 31, wherein the second transistor comprises the second gate electrode over the substrate containing the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode which are electrically connected to the oxide semiconductor layer.

35. The semiconductor device according to claim 31, wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

36. The semiconductor device according to claim 31, wherein the semiconductor material is silicon.

37. The semiconductor device according to claim 31, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

38. The semiconductor device according to claim 31, wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

39. The semiconductor device according to claim 31, wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

40. The semiconductor device according to claim 31, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.