DISPLAY DEVICE

• US 20110121300A1
• Filed: 11/17/2010
• Published: 05/26/2011
• Est. Priority Date: 11/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isa, Toshiyuki, Miyairi, Hidekazu
• Granted Patent: US 8,395,156 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a display device whose frame can be narrowed and whose display characteristics are excellent. The display device includes a driver circuit and a pixel portion. The driver circuit and the pixel portion are formed using a dual-gate thin film transistor and a single-gate thin film transistor, respectively. In the dual-gate thin film transistor in the display device, a semiconductor layer is formed using a microcrystalline semiconductor region and a pair of amorphous semiconductor regions, and a gate insulating layer and an insulating layer are in contact with the microcrystalline semiconductor region of the semiconductor layer.

Claims

1. A display device comprising:

a substrate;

a pixel portion including a single-gate transistor, the single-gate transistor comprising;

a first gate electrode over the substrate;

a gate insulating layer over the first gate electrode;

a first semiconductor layer over the gate insulating layer, the first semiconductor layer comprising;

a first microcrystalline semiconductor region over the gate insulating layer; and

a first amorphous semiconductor region over the first microcrystalline semiconductor region,

a pair of first wirings over the first amorphous semiconductor region; and

an insulating layer over the pair of first wirings and the first amorphous semiconductor region,

a driver circuit including a dual-gate transistor, the dual-gate transistor comprising;

a second gate electrode over the substrate;

the gate insulating layer over the second gate electrode;

a second semiconductor layer over the gate insulating layer, the second semiconductor layer comprising;

a second microcrystalline semiconductor region over the gate insulating layer; and

a pair of second amorphous semiconductor regions over the second microcrystalline semiconductor region,

a pair of second wirings over the pair of second amorphous semiconductor regions;

the insulating layer over the pair of second wirings and the second microcrystalline semiconductor region; and

a back gate electrode over the insulating layer.

2. The display device according to claim 1,

wherein the first microcrystalline semiconductor region has a first projected portion whose tip is narrowed from the gate insulating layer toward the first amorphous semiconductor region, and

wherein the second microcrystalline semiconductor region has a second projected portion whose tip is narrowed from the gate insulating layer toward the pair of second amorphous semiconductor regions.

3. The display device according to claim 2, wherein the each tip of the first projected portion and the second projected portion has an obtuse angle.

4. The display device according to claim 1, wherein semiconductor crystal grains are included in the first amorphous semiconductor region and the pair of second amorphous semiconductor regions.

5. The display device according to claim 1,

wherein the single-gate transistor further comprises a pair of first impurity regions provided between the first amorphous semiconductor region and the pair of first wirings, and

wherein the dual-gate transistor further comprises a pair of second impurity regions provided between the pair of second amorphous semiconductor regions and the pair of second wirings.

6. The display device according to claim 1,

wherein the pair of first wirings are in contact with a side surface of the first microcrystalline semiconductor region and a side surface of the first amorphous semiconductor region, and

wherein the pair of second wirings are in contact with a side surface of the second microcrystalline semiconductor region and a side surface of the pair of second amorphous semiconductor regions.

7. A display device comprising:

a substrate;

a pixel portion including a single-gate transistor, the single-gate transistor comprising;

a first gate electrode over the substrate;

a gate insulating layer over the first gate electrode;

a first semiconductor layer over the gate insulating layer, the first semiconductor layer comprising;

a first microcrystalline semiconductor region over the gate insulating layer; and

a first amorphous semiconductor region over the first microcrystalline semiconductor region,

a pair of first wirings over the first amorphous semiconductor region; and

an insulating layer over the pair of first wirings and the first amorphous semiconductor region,

a driver circuit including a dual-gate transistor, the dual-gate transistor comprising;

a second gate electrode over the substrate;

the gate insulating layer over the second gate electrode;

a second semiconductor layer over the gate insulating layer, the second semiconductor layer comprising;

a second microcrystalline semiconductor region over the gate insulating layer; and

a pair of second amorphous semiconductor regions over the second microcrystalline semiconductor region,

a pair of second wirings over the pair of second amorphous semiconductor regions;

the insulating layer over the pair of second wirings and the second microcrystalline semiconductor region; and

a back gate electrode over the insulating layer,

wherein the first gate electrode is wider than the first microcrystalline semiconductor region and the first amorphous semiconductor region.

8. The display device according to claim 7,

wherein the first microcrystalline semiconductor region has a first projected portion whose tip is narrowed from the gate insulating layer toward the first amorphous semiconductor region, and

wherein the second microcrystalline semiconductor region has a second projected portion whose tip is narrowed from the gate insulating layer toward the pair of second amorphous semiconductor regions.

9. The display device according to claim 8, wherein the each tip of the first projected portion and the second projected portion has an obtuse angle.

10. The display device according to claim 7, wherein semiconductor crystal grains are included in the first amorphous semiconductor region and the pair of second amorphous semiconductor regions.

11. The display device according to claim 7,

wherein the single-gate transistor further comprises a pair of first impurity regions provided between the first amorphous semiconductor region and the pair of first wirings, and

wherein the dual-gate transistor further comprises a pair of second impurity regions provided between the pair of second amorphous semiconductor regions and the pair of second wirings.

12. The display device according to claim 7,

wherein the pair of first wirings are in contact with a side surface of the first microcrystalline semiconductor region and a side surface of the first amorphous semiconductor region, and

wherein the pair of second wirings are in contact with a side surface of the second microcrystalline semiconductor region and a side surface of the pair of second amorphous semiconductor regions.

13. A display device comprising:

a substrate;

a pixel portion including a single-gate transistor, the single-gate transistor comprising;

a first gate electrode over the substrate;

a gate insulating layer over the first gate electrode;

a first semiconductor layer over the gate insulating layer, the first semiconductor layer comprising;

a first microcrystalline semiconductor region over the gate insulating layer; and

a first amorphous semiconductor region over the first microcrystalline semiconductor region,

a pair of first wirings over the first amorphous semiconductor region; and

an insulating layer over the pair of first wirings and the first amorphous semiconductor region,

a driver circuit including a dual-gate transistor, the dual-gate transistor comprising;

a second gate electrode over the substrate;

the gate insulating layer over the second gate electrode;

a second semiconductor layer over the gate insulating layer, the second semiconductor layer comprising;

a second microcrystalline semiconductor region over the gate insulating layer; and

a pair of second amorphous semiconductor regions over the second microcrystalline semiconductor region,

a pair of second wirings over the pair of second amorphous semiconductor regions;

the insulating layer over the pair of second wirings and the second microcrystalline semiconductor region; and

a back gate electrode over the insulating layer,

wherein the second gate electrode is electrically connected to the back gate electrode.

14. The display device according to claim 13,

wherein the first microcrystalline semiconductor region has a first projected portion whose tip is narrowed from the gate insulating layer toward the first amorphous semiconductor region, and

wherein the second microcrystalline semiconductor region has a second projected portion whose tip is narrowed from the gate insulating layer toward the pair of second amorphous semiconductor regions.

15. The display device according to claim 14, wherein the each tip of the first projected portion and the second projected portion has an obtuse angle.

16. The display device according to claim 13, wherein semiconductor crystal grains are included in the first amorphous semiconductor region and the pair of second amorphous semiconductor regions.

17. The display device according to claim 13,

wherein the single-gate transistor further comprises a pair of first impurity regions provided between the first amorphous semiconductor region and the pair of first wirings, and

wherein the dual-gate transistor further comprises a pair of second impurity regions provided between the pair of second amorphous semiconductor regions and the pair of second wirings.

18. The display device according to claim 13,

wherein the pair of first wirings are in contact with a side surface of the first microcrystalline semiconductor region and a side surface of the first amorphous semiconductor region, and

wherein the pair of second wirings are in contact with a side surface of the second microcrystalline semiconductor region and a side surface of the pair of second amorphous semiconductor regions.