LED with Improved Injection Efficiency

• US 20110121357A1
• Filed: 11/25/2009
• Published: 05/26/2011
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Toshiba Techno Center Inc. (Toshiba Corporation)
• Inventors: Wu, Jun, Lester, Steven, Ramer, Jeff, Zhang, Ling
• Granted Patent: US 8,525,221 B2
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 33/0004 Devices characterised by their operation
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Claims

1. A light emitting device comprising:

a p-type semiconductor layer comprising a p-type semiconductor material;

an n-type semiconductor layer comprising an n-type semiconductor material; and

an active layer sandwiched between said p-type and n-type semiconductor layers, said active layer emitting light when holes from said p-type semiconductor layer combine with electrons from said n-type semiconductor layer therein, said active layer comprising a plurality of sub-layers, said active layer having a plurality of pits in which side surfaces of a plurality of said sub-layers are in contact with said p-type semiconductor material such that holes from said p-type semiconductor material are injected into those sub-layers through said exposed side surfaces without passing through another sub-layer.

2. The light emitting device of claim 1 wherein said plurality of sub-layers comprises a stack of substantially planar layers having openings at said pits, each sub-layer comprising a substantially planar surface that is in contact with said substantially planar surface of another of said sub-layers and a plurality of side surfaces, each side surface being bounded by a wall of one of said pits, each sub-layer being characterized by a first hole current that enters that sub-layer through said substantially planar surface and a second hole current that enters that sub-layer through said side surfaces of said sub-layer, said second hole current being greater than 10 percent of said first hole current for at least one of said sub-layers.

3. The light emitting device of claim 1 wherein said pits are characterized by a pit density, said pit density being between 10⁷ cm⁻

2 and 10¹⁰ cm<sup>−

2</sup>.

4. The light emitting device of claim 1 wherein said first and second semiconductor layers comprise GaN family materials.

5. The light emitting device of claim 1 wherein said pits are located at dislocations in said n-type semiconductor layer.

6. A method for fabricating a light emitting device comprising:

growing an epitaxial n-type semiconductor layer on a substrate;

growing an active layer comprising a plurality of sub-layers on said n-type semiconductor layer under growth conditions that cause pits to form in said active layer, a plurality of said sub-layers having sidewalls that are bounded by said pits;

etching said active layer to expose sidewalls of said sub-layers in said pits;

growing an epitaxial p-type semiconductor layer over said active layer such that said p-type semiconductor layer extends into said pits and contacts said sidewalls of said sub-layers; and

providing contacts for applying a potential difference between said p-type semiconductor layer and said n-type semiconductor layer.

7. The method of claim 6 wherein said n-type semiconductor layer has a lattice constant that is different from that of said n-type semiconductor layer, said difference giving rise to dislocations and wherein said pits are formed at locations having said dislocations.

8. The method of claim 6 wherein etching said active layer to expose said sidewalls comprises changing a gas composition in an epitaxial growth chamber in which said device is being fabricated to an atmosphere that etches facets of said active layer exposed in said pits faster than facets of said active layer that are not exposed in said pits.

9. The method of claim 6 wherein said active layer is grown on a c-plane facet of a material in a GaN family of materials and wherein etching said active layer to expose said sidewalls comprises chemically etching said active layer with an etchant that etches crystal facets in said pits faster than material on said c-plane facet.

10. The method of claim 8 wherein said atmosphere comprises NH₃ and/or H₂.

11. The method of claim 7 wherein said n-type semiconductor layer is grown under conditions that result in a density of dislocations between 10⁷ cm⁻

2 and 10¹⁰ cm<sup>−

2</sup>.

12. The method of claim 6 wherein etching said active layer to expose said sidewalls comprises etching one of said sub-layers after that sub-layer has been deposited to expose said sidewalls of that sub-layer in said pits prior to depositing another sub-layer on that sub-layer.