TRENCH-GATE SEMICONDUCTOR DEVICE

• US 20110121384A1
• Filed: 07/27/2009
• Published: 05/26/2011
• Est. Priority Date: 07/25/2008
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Peake, Steven Thomas, Rutter, Phil
• Granted Patent: US 8,901,638 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate semiconductor device is disclosed, in which the p-layer (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The re-placement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region. The invention does not require a RESURF device structure, so has wide process windows, since the dopant levels and layer thicknesses do not have to be controlled to provide charge balancing.

Claims

1. A trench-gate semiconductor device comprising

a semiconductor body having a major surface defining a plane,

a trench extending into the semiconductor from the major surface and having sidewalls and having therein a conductive gate and a field plate,

the conductive gate having a bottom level which is a first distance from the plane, the conductive gate being spaced apart from the sidewalls by a first gate oxide layer of a first thickness,

the field plate being more remote from the plane than is the conductive gate, and being spaced apart from the sidewalls by a second gate oxide layer of a second thickness which is thicker than the first thickness,

a first region of a first conductivity type adjacent the trench at the major surface,

a second region of the first conductivity type and having a first doping level of a first dopant and spaced apart from the first region by a gap,

and a channel-accommodating region of a second conductivity type therebetween filling the gap, the channel-accommodating region having a first layer which has a second doping level of a second dopant and a second layer which is more remote from the surface than the first layer and which has a third doping level of a third dopant, the first layer being adjacent the second layer adjacent the trench at a second distance from the plane which is less than the first distance,

the channel-accommodating region being adjacent the second region at a third distance from the plane,

wherein the channel-accommodating region is adjacent the trench across the whole of the gap,

the third distance is greater than the first distance,

and the third doping level is such that, in operation, when a reverse bias is applied across the trench-gate semiconductor device, at least 30% of the bias is across the channel accommodating region.

2. A trench-gate semiconductor device according to claim 1, wherein, when a reverse bias is applied across the trench-gate semiconductor device, at least half the bias is across the channel-accommodating region.

3. A trench-gate semiconductor device according to claim 1, wherein the field plate is electrically connected to the conductive gate.

4. A trench-gate semiconductor device according to claim 1, wherein the field plate is electrically connected to a source contact.

5. A trench-gate semiconductor device according to claim 1, wherein the field plate is electrically connected to a fixed bias voltage.

6. A trench-gate semiconductor device according to claim 1, wherein the third doping level is in the range 1E15/cm3 to 5E15/cm3.

7. A trench-gate semiconductor device according to claim 1, wherein the third doping level is less than or equal to 1E15/cm3.

8. A trench-gate semiconductor device according to claim 1, wherein the first doping level is in the range 5E16/cm3 to 5E17/cm3.

9. A trench-gate semiconductor device according to claim 1, wherein the second dopant is the same as the third dopant.

10. A trench-gate semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.