SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20110121388A1
• Filed: 02/08/2011
• Published: 05/26/2011
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: CHOI, Shin Gyu, OH, Seung Chul
• Granted Patent: US 8,933,509 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.

Claims

1-22. -22. (canceled)

23. A semiconductor device comprising:

a device isolation structure formed in a semiconductor substrate, the device isolation structure defining an active region;

a recess channel structure disposed in the semiconductor substrate under the active region;

a first lower gate conductive layer conformal to the recess channel structure and defining a recess;

a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, the holding layer configured to hold a shift of a seam occurring in the recess channel structure; and

a second lower gate conductive layer over and directly contacting the first lower gate conductive layer and the holding layer.

24. The semiconductor device according to claim 23, wherein the recess channel structure includes an upper recess channel structure and a lower recess channel structure, the lower recess channel structure having a latitudinal width greater than that of the upper recess channel structure.

27. The semiconductor device according to claim 23, wherein the first lower gate conductive layer includes a polysilicon layer doped with impurity ions.

28. The semiconductor device according to claim 27, wherein the polysilicon layer doped with impurity ions is amorphous.

29. The semiconductor device according to claim 28, wherein the impurity ions include phosphorous (P) with a concentration in the range of about 1.0E20 ions/cm³ to about 4.0E20 ions/cm³.

30. The semiconductor device according to claim 23, wherein the second lower gate conductive layer includes a polysilicon layer doped with impurity ions.

31. The semiconductor device according to claim 30, wherein the impurity ions include boron (B) or phosphorous (P) with a concentration in the range of about 1.0E15 ions/cm³ to about 7.0E15 ions/cm³.

32. The semiconductor device according to claim 31, wherein the second lower gate conductive layer in a PMOS region is formed of the polysilicon layer doped with boron (B).

33. The semiconductor device according to claim 31, wherein the second lower gate conductive layer in a NMOS region is formed of the polysilicon layer doped with phosphorous (P).

34. The semiconductor device according to claim 23, wherein the holding layer is selected from the group consisting of an insulating film, a metal film, a conductive layer, and combinations thereof.

35. The semiconductor device according to claim 34, wherein the holding layer is an oxide film or a crystalline polysilicon layer.

36. The semiconductor device according to claim 23, further comprising a gate insulating film disposed at the interface between the gate electrode and the semiconductor substrate including the recess channel structure.

37. The semiconductor device according to claim 23, further comprising a gate hard mask layer pattern disposed over the second lower gate conductive layer.

25. (canceled)

26. (canceled)

38. A semiconductor device comprising:

a device isolation structure formed in a semiconductor substrate having a PMOS region and a NMOS region, the device isolation structure defining an active region;

a bulb-type recess channel structure disposed in the semiconductor substrate under the active region; and

a lower gate electrode disposed over the active region, the lower gate electrode including a stacked structure having a first lower gate conductive layer, a holding layer, and a second lower gate conductive layer to fill the bulb-type recess channel structure, wherein the first lower gate conductive layer is formed of a polysilicon layer doped with impurity ions, the holding layer prevents a seam and a shift of the seam occurring in the bulb-type recess channel structure, and the second lower gate conductive layer is formed of a polysilicon layer doped with impurity ions wherein the impurity ions in the PMOS region and the NMOS region are different.