ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION

• US 20110121395A1
• Filed: 11/23/2010
• Published: 05/26/2011
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: BauaBTech Company
• Original Assignee: BauaBTech Company
• Inventors: Kim, Kilho
• Granted Patent: US 8,324,688 B2
• Time in Patent Office: Days
• US Class Current: 257/361
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/7408 the device being a capacitor or a resistor
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation. The ESD protection device includes protection device includes: a high voltage P well formed in a semiconductor substrate, an N-drift region formed in the high voltage P well, an anode N+ diffusion region and an anode P+ diffusion region formed in the N-drift region, a buffer N+ diffusion region formed in the N-drift region and separated a predetermined distant from the anode N+ diffusion region, a buffer N-ballistic region surrounding the buffer N+ diffusion region, an anode N-ballistic region surrounding the anode N+ diffusion region and the anode P+ diffusion region, a cathode N+ diffusion region and a cathode P+ diffusion region formed in the high voltage P well and separated a predetermined distance from the N-drift region, a MOSFET gate disposed on the semiconductor substrate between the cathode N+ diffusion region and the N-drift region, and a capacitor electrode disposed on the semiconductor substrate between the anode N+ diffusion region and the buffer N+ diffusion region.

Claims

1. An electrostatic discharge (ESD) protection device, comprising:

a high voltage P well formed in a semiconductor substrate;

an N-drift region formed in the high voltage P well;

an anode N+ diffusion region and an anode P+ diffusion region formed in the N-drift region;

a buffer N+ diffusion region formed in the N-drift region and separated a predetermined distant from the anode N+ diffusion region;

a buffer N-ballistic region surrounding the buffer N+ diffusion region;

an anode N-ballistic region surrounding the anode N+ diffusion region and the anode P+ diffusion region;

a cathode N+ diffusion region and a cathode P+ diffusion region formed in the high voltage P well and separated a predetermined distance from the N-drift region;

a MOSFET gate disposed on the semiconductor substrate between the cathode N+ diffusion region and the N-drift region; and

a capacitor electrode disposed on the semiconductor substrate between the anode N+ diffusion region and the buffer N+ diffusion region.

2. The ESD protection device according to claim 1, further comprising:

a resistor polysilicon layer on the semiconductor layer outside the high voltage P well.

3. The ESD protection device according to claim 1, wherein the buffer N-ballistic region is formed at a density of 10¹³˜

10¹⁴ ions/cm³ to pass through the N-drift region in a depth direction.

4. The ESD protection device according to claim 1, wherein the anode N-ballistic region is formed at a density of 10¹³˜

10¹⁴ ions/cm³ to pass through the N-drift region in a depth direction.

5. The ESD protection device according to claim 1, wherein the anode N+ diffusion region and the anode P+ diffusion region are connected together to constitute an anode, or only the anode P+ diffusion region is connected to constitute the anode without directly connecting the anode N+ diffusion region.

6. The ESD protection device according to claim 2, wherein the capacitor electrode, the MOSFET gate and the resistor polysilicon layer are connected at one end thereof to one another and the other end of the resistor polysilicon layer is connected to a cathode, such that a DDDNMOS gate formed in an HVOHORGCR device is coupled to an anode through a capacitor and is coupled to the cathode through a resistor.

7. The ESD protection device according to claim 6, further comprising:

at least one diode connected in series between a terminal to which the cathode N+ diffusion region and the cathode P+ diffusion region are connected and a cathode terminal.

8. The ESD protection device according to claim 6, further comprising:

a P-type MOSFET connected in series between a terminal to which the cathode N+ diffusion region and the cathode P+ diffusion region are connected and a cathode terminal.

9. An electrostatic discharge (ESD) protection device comprising:

an N-drift region formed in a semiconductor substrate;

an anode N+ diffusion region and an anode P+ diffusion region formed in the N-drift region;

a buffer N+ diffusion region formed in the N-drift region and separated a predetermined distant from the anode N+ diffusion region;

a buffer N-ballistic region surrounding the buffer N+ diffusion region;

an anode N-ballistic region surrounding the anode N+ diffusion region and the anode P+ diffusion region;

a cathode N+ diffusion region and a cathode P+ diffusion region formed in the semiconductor substrate outside the N-drift region and separated a predetermined distance from the N-drift region;

a high voltage P well surrounding the cathode N+ diffusion region and the cathode P+ diffusion region with one side of the high voltage P well disposed between the anode N-ballistic region and the buffer N-ballistic region;

a MOSFET gate disposed on the semiconductor substrate between the cathode N+ diffusion region and the N-drift region; and

a capacitor electrode disposed on the semiconductor substrate between the anode N+ diffusion region and the buffer N+ diffusion region.

10. The ESD protection device according to claim 9, further comprising:

a resistor polysilicon layer on the semiconductor layer outside the high voltage P well.

11. The ESD protection device according to claim 9, wherein the buffer N-ballistic region is formed at a density of 10¹³˜

10¹⁴ ions/cm³ to pass through the N-drift region in a depth direction.

12. The ESD protection device according to claim 9, wherein the anode N-ballistic region is formed at a density of 10¹³˜

10¹⁴ ions/cm³ to pass through the N-drift region in a depth direction.

13. The ESD protection device according to claim 9, wherein the anode N+ diffusion region and the anode P+ diffusion region are connected together to constitute an anode, or only the anode P+ diffusion region is connected to constitute the anode without directly connecting the anode N+ diffusion region.

14. The ESD protection device according to claim 10, wherein the capacitor electrode, the MOSFET gate and the resistor polysilicon layer are connected at one end thereof to one another and the other end of the resistor polysilicon layer is connected to a cathode, such that a DDDNMOS gate formed in an HVOHORGCR device is coupled to an anode through a capacitor and is coupled to the cathode through a resistor.

15. The ESD protection device according to claim 14, further comprising:

at least one diode connected in series between a terminal to which the cathode N+ diffusion region and the cathode P+ diffusion region are connected and a cathode terminal.

16. The ESD protection device according to claim 14, further comprising:

a P-type MOSFET connected in series between a terminal to which the cathode N+ diffusion region and the cathode P+ diffusion region are connected and a cathode terminal.