PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE

• US 20110121412A1
• Filed: 01/31/2011
• Published: 05/26/2011
• Est. Priority Date: 03/09/2007
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Howe, Roger T., Quevy, Emmanuel P., Monadgemi, Pezhman
• Granted Patent: US 8,288,835 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/0721 Forming the micromechanical structure with a low-temperature process B81C2203/0735 takes precedence
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure

Abstract

Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.

Claims

1. A microshell comprising:

a perforated pre-sealing layer to partially enclose a chamber on a substrate,

wherein the pre-sealing layer further comprises an integrated getter layer disposed between other layers of the perforated pre-sealing layer; and

a sealing layer on the pre-sealing layer to close the perforation.

2. The microshell of claim 1, wherein the getter layer is titanium.

3. The microshell of claim 1, wherein the pre-sealing layer has a planar top surface and the getter layer is non-planar.

4. The microshell of claim 1, wherein the getter layer is between a first and second layer of a dielectric material.

5. The microshell of claim 4, wherein the first layer has a thickness less than the thickness of the second layer.

6. The microshell of claim 4, wherein the first layer is an oxide of silicon

7. The microshell of claim 4, wherein the first layer is permeable.

8. The microshell of claim 1, wherein the getter layer is electrically coupled to a ground ring adjacent to the metal-insulator microshell.

9. The microshell of claim 1, wherein the getter layer is a continuous film surrounding the perforation.

10. A method of forming a microshell over a substrate comprising:

forming a sacrificial layer over the substrate;

forming a pre-sealing layer on the sacrificial layer, the pre-sealing layer comprising a first layer formed on the sacrificial layer, a getter layer formed on the first layer, and a second layer formed on the getter layer;

perforating the layers of the pre-sealing layer to expose the sacrificial layer;

removing the sacrificial layer to form a chamber around a device under the pre-sealing layer; and

sealing the perforated pre-sealing layer.

11. The method of claim 10, the first layer of the pre-sealing layer being a permeable layer.

12. The method of claim 10, wherein forming a sacrificial layer further comprises:

depositing a sacrificial material over the substrate;

etching the sacrificial material with a first mask to define an edge of the chamber;

etching the sacrificial material with a second mask to form an isolated sacrificial layer having a blade of sacrificial material extending upwards from the substrate.

13. The method of claim 12, wherein forming the getter layer on the first layer further comprises depositing a getter material adjacent to the sidewalls of the blade of sacrificial material to increase the surface area of the getter layer.

14. The method of claim 10, wherein perforating the layers of the pre-sealing layer further comprises planarizing the pre-sealing layer to perforate the layers of the pre-sealing layer with a topographic feature of the sacrificial layer.

15. The method of claim 10, wherein sealing the pre-sealing layer further comprises:

nonconformally depositing a dielectric to occlude the perforation; and

depositing a metal to hermetically seal the perforated pre-sealing layer.

16. The method of claim 15, wherein the chamber is heated for at least 30 seconds to a temperature above 400°

C. before depositing the dielectric to desorb contaminants.

17. The method of claim 15, wherein the dielectric is deposited with the substrate tilted by a small angle relative to a predominant ion flux in the deposition chamber to reduce back-deposition of the sealing material.

18. The method of claim 10, further comprising:

etching through the sealing layer to expose a metal ground ring adjacent to the chamber; and

depositing a conductive layer on the sealing layer and ground ring to electrically ground the microshell.

19. The method of claim 18, further comprising:

depositing a semiconductor over the conductive layer to structurally reinforce the microshell.

20. The method of claim 19, wherein the semiconductor comprises germanium to form a germanosilicide