METHOD AND APPARATUS FOR INCREASED EFFECTIVENESS OF DELAY AND TRANSISTION FAULT TESTING

• US 20110121838A1
• Filed: 11/25/2009
• Published: 05/26/2011
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Gillis, Pamela S., Smith, Jack R., Wilder, Tad J., Woytowich, Francis, Xia, Tian
• Granted Patent: US 8,381,050 B2
• Time in Patent Office: Days
• US Class Current: 324/537
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

Claims

1. A method of delay fault testing integrated circuits comprising:

creating a plurality of test clock gating groups, said plurality of test clock gating groups comprising elements defining inter-element signal paths within said integrated circuit, each of the elements of said plurality of test clock gating groups sharing clock frequency and additional shared characteristics; and

commonly and selectively connecting at least one test signal through at least one low-speed gate transistor to each of said elements comprising each of the plurality of test clock gating groups based on membership in said test clock gating group.

2. The method of claim 1, wherein the shared additional characteristics comprise at least one of:

latency, skew and cross-domain inter-element signal paths.

3. The method of claim 1, wherein at least one of said elements of said integrated circuit are based on a plurality of pre-designed cores and said connecting of at least one test signal to at least one of said plurality of pre-designed cores is enabled with a single gate.

4. The method of claim 1, wherein at least two of said elements are slow logic elements which are selectively enabled by a single gate.

5. The method of claim 1, wherein at least two of said elements are multi-cycle elements which are selectively enabled by a single gate.

6. The method of claim 1, further comprising:

programming an on-chip programmable delay line for a launch time of at least one pattern generator, said launch time based on a simulation of delays in said inter-element signal paths and a tap selection of said on-chip programmable delay line;

generating a test pattern based on said launch time; and

indicating the result of a comparison between a test pattern received over the inter-element signal path to said generated test pattern.

7. The method of claim 6, wherein at least one of said plurality of pre-designed cores is implemented using field programmable gate arrays.

22. The method of claim 6, further comprising verifying the proper functioning of the programmable delay line based on the further steps of:

forming an oscillator loop with an output;

programming said on-chip delay line based on a second tap setting;

measuring an oscillating frequency at said output of the oscillator loop;

identifying an expected oscillating frequency based on said tap setting;

comparing said measured oscillating frequency to said expected oscillating frequency;

indicating a proper functioning of the programmable delay line based on said comparison.

23. The method of claim 1, further comprising:

programming an on-chip programmable delay line to create a high precision test clock for a launch time of at least one pattern generator, said launch time based on an optimal tap selection of said on-chip programmable delay line based on a simulation of a routed design of said inter-elements;

generating a test pattern based on said launch time; and

indicating the result of a comparison between a test pattern received over the inter-element signal path to said generated test pattern.

24. The method of claim 6, wherein a routing of the inter-element signal paths is maintained under test.

25. The method of claim 6, further comprising grouping inter-element signal paths into a plurality of independent groups based on common elements and selecting paths from said plurality of independent groups enabling simultaneous testing.

8. A method of delay fault testing integrated circuits comprising:

creating a plurality of scan-enable gating groups, said plurality of scan-enable gating groups comprising elements defining inter-element signal paths within said integrated circuit, each of the elements of said plurality of scan-enable gating groups sharing clock frequency and additional shared characteristics; and

commonly and selectively connecting at least one test signal through at least one low-speed gate transistor to said elements comprising the plurality of scan-enable gating groups using low-speed gating and based on membership in said scan-enable gating group.

9. The method of claim 8, further comprising:

programming an on-chip programmable delay line for a launch time of at least one pattern generator, said launch time based on a simulation of delays in said inter-element signal paths and a tap selection of said on-chip programmable delay line;

generating a test pattern based on said launch time; and

indicating the result of a comparison between a test pattern received over the inter-element signal path to said generated test pattern.

10. The method of claim 9, wherein at least one of said plurality of pre-designed cores is implemented using field programmable gate arrays.

11. An integrated circuit structure comprising:

a plurality of scan-enable gating groups, said plurality of scan-enable gating groups comprising elements defining inter-element signal paths within said integrated circuit, each of the elements of said plurality of scan-enable gating groups sharing clock frequency and additional shared characteristics; and

at least one low-speed gate transistor commonly and selectively connecting at least one test signal through to said elements;

said elements comprising the plurality of scan-enable gating groups;

said low speed gate transistor connected based on said elements membership in said scan-enable gating group.

12. The integrated circuit of claim 11, wherein the shared additional characteristics comprise at least one of:

latency, skew and cross-domain inter-element signal paths.

13. The integrated circuit of claim 11, wherein at least one of said elements of said integrated circuit are based on a plurality of pre-designed cores and said gating of at least one test signal to at least one of said plurality of pre-designed cores is enabled with a single gate.

14. The integrated circuit of claim 11, wherein at least two of said elements are slow logic elements which are selectively enabled by a single gate.

15. The integrated circuit of claim 11, wherein at least two of said elements are multi-cycle elements which are selectively enabled by a single gate.

16. The integrated circuit built-in self-test structures of claim 11, further comprising:

at least one test pattern generator for generating a test pattern over at least one of said inter-element signal paths;

an on-chip programmable delay line for programming a delayed launch time for said at least one pattern generator, said launch time based on delays predicted in said at least one inter-element signal paths, said delayed launch time based on a tap selection of said on-chip programmable delay line; and

an output result analyzer that indicates the result of a comparison between a test pattern received over at least one of the inter-element signal path and said generated test pattern.

17. The integrated circuit of claim 16, wherein at least one of said plurality of pre-designed cores is implemented using field programmable gate arrays.

18. An integrated circuit with built-in self test structures comprising:

low speed gates for commonly and selectively gating at least one test signal to elements comprising a plurality of scan-enable gating groups, said scan-enable gating groups comprised of elements defining inter-element signal paths and sharing clock frequency and additional characteristics.

19. The integrated circuit built-in self-test structures of claim 18, further comprising:

at least one test pattern generator for generating a test pattern over at least one of said inter-element signal paths;

an on-chip programmable delay line for programming a delayed launch time for said at least one pattern generator, said launch time based on delays predicted in said at least one inter-element signal paths, said delayed launch time based on a tap selection of said on-chip programmable delay line; and

an output result analyzer that indicates the result of a comparison between a test pattern received over at least one the inter-element signal path and said generated test pattern.

20. The integrated circuit of claim 19, wherein at least one of said plurality of pre-designed cores is implemented using field programmable gate arrays.

21. A program storage device readable by machine tangibly embodying a program of instructions executable by said machine for performing a method of delay fault testing of integrated circuits comprising the steps of:

creating a plurality of test clock gating groups, said plurality of test clock gating groups comprising elements defining inter-element signal paths within said integrated circuit, each of the elements of said plurality of test clock gating groups sharing clock frequency and additional shared characteristics; and

commonly and selectively connecting at least one test signal through at least one low-speed gate transistor to each of said elements comprising each of the plurality of test clock gating groups based on membership in said test clock gating group.