SYSTEMS AND METHODS FOR DETECTING INTERFERENCE IN AN INTEGRATED CIRCUIT

• US 20110121865A1
• Filed: 11/25/2009
• Published: 05/26/2011
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Olmos, Alfredo, Maltione, Ricardo, da Silva, Eduardo Riberiro
• Granted Patent: US 8,330,502 B2
• Time in Patent Office: Days
• US Class Current: 327/77
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.

Claims

1. An integrated circuit comprising:

a sensing arrangement configured to sense an interference signal; and

an interference detection module coupled to the sensing arrangement, wherein the interference detection module is configured to detect when a power level associated with the interference signal is greater than a first threshold value.

2. The integrated circuit of claim 1, wherein the sensing arrangement comprises:

a sensing element sensitive to electromagnetic interference; and

a capacitive element coupled between the sensing element and the interference detection module.

3. The integrated circuit of claim 2, wherein the sensing element comprises a conductive trace.

4. The integrated circuit of claim 2, further comprising a plurality of pins for interfacing with the integrated circuit, wherein the sensing element comprises a first pin of the plurality of pins.

5. The integrated circuit of claim 1, further comprising a semiconductor substrate, wherein the sensing arrangement and the interference detection module are formed on the semiconductor substrate and encapsulated in a single device package.

6. The integrated circuit of claim 5, wherein the sensing arrangement comprises a first conductive structure overlying the semiconductor substrate and coupled to the interference detection module.

7. The integrated circuit of claim 6, wherein the sensing arrangement further comprises a dielectric material overlying the semiconductor substrate, wherein the first conductive structure overlies the dielectric material.

8. The integrated circuit of claim 5, further comprising a leadframe pad affixed to a surface of the semiconductor substrate, wherein the sensing arrangement comprises a capacitive element coupled between the leadframe pad and the interference detection module.

9. The integrated circuit of claim 1, wherein the interference detection module comprises:

comparison circuitry coupled to the sensing arrangement, the comparison circuitry being configured to detect when the power level associated with the interference signal is greater than the first threshold value; and

a filtering arrangement coupled to the comparison circuitry, the filtering arrangement being configured to indicate when the power level associated with the interference signal is greater than the first threshold value for a predetermined amount of time.

10. The integrated circuit of claim 1, further comprising:

analog circuitry having a bias point, the bias point controlling an operating characteristic of the analog circuitry; and

a voltage regulator coupled to the analog circuitry and the interference detection module, wherein the voltage regulator is configured to adjust the bias point of the analog circuitry when the detected power level of the interference signal is greater than the first threshold value.

11. The integrated circuit of claim 1, further comprising a processing system coupled to the interference detection module, wherein:

the interference detection module is configured to generate an interrupt for the processing system when the power level associated with the interference signal is greater than the first threshold value; and

the processing system is configured to take remedial action in response to the interrupt.

12. A method for providing protection from electromagnetic interference in an integrated circuit, the method comprising:

sensing electromagnetic interference within the integrated circuit, resulting in a sensed interference signal;

detecting an interference event based on a power level associated with the sensed interference signal; and

taking remedial action in response to the interference event.

13. The method of claim 12, wherein detecting the interference event comprises:

comparing the power level of the sensed interference signal to a first threshold value; and

identifying the interference event when the power level exceeds the first threshold value.

14. The method of claim 13, further comprising:

sensing a second electromagnetic interference signal within the integrated circuit, resulting in a second sensed interference signal;

determining a second power level associated with the second sensed interference signal;

comparing the second power level of the second sensed interference signal to a second threshold value, the second threshold value being greater than the first threshold value; and

identifying a second interference event when the second power level exceeds the second threshold value.

15. The method of claim 12, the integrated circuit including analog circuitry, wherein taking remedial action comprises adjusting a bias point of the analog circuitry in response to the interference event.

16. The method of claim 12, further comprising generating a first interrupt for a processing system of the integrated circuit in response to the interference event, wherein the processing system is configured to take remedial action in response to the first interrupt.

17. An interference protection system for use with an integrated circuit package, the interference protection system comprising:

a sensing arrangement configured to obtain an interference signal in response to electromagnetic interference within the integrated circuit package; and

an interference detection module coupled to the sensing arrangement, wherein the interference detection module is configured to;

identify an interference event based on the interference signal; and

indicate the interference event.

18. The interference protection system of claim 17, further comprising a processing system contained in the integrated circuit package, wherein:

the interference detection module is coupled to the processing system and configured to generate an interrupt signal for the processing system in response to the interference event; and

the processing system is configured to take remedial action in response to the interrupt signal.

19. The interference protection system of claim 17, further comprising a semiconductor substrate, wherein the sensing arrangement comprises:

a conductive trace formed on the semiconductor substrate; and

a capacitive element coupled between the conductive trace and the interference detection module.

20. The interference protection system of claim 17, further comprising a semiconductor substrate, wherein the sensing arrangement comprises:

a first conductive material overlying the semiconductor substrate, wherein the first conductive material and the semiconductor substrate are electrically connected;

a dielectric material overlying the first conductive material; and

a second conductive material overlying the dielectric material, wherein the second conductive material is coupled to the interference detection module.