PHASE LOCKED LOOP APPARATUS WITH SELECTABLE CAPACITANCE DEVICE

• US 20110121910A1
• Filed: 11/20/2009
• Published: 05/26/2011
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yang, Bo, Muthali, Harish S., Barnett, Kenneth C.
• Granted Patent: US 8,098,110 B2
• Time in Patent Office: Days
• US Class Current: 331/36.C
• CPC Class Codes: H03L 1/023 by using voltage variable capacitance diodes
• CPC Class Codes: H03L 2207/05 Compensating for non-linear characteristics of the controlled oscillator
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals

Abstract

A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Claims

1. A phase locked loop (PLL) apparatus comprising:

an oscillator configured to generate an oscillator signal;

a variable capacitance device connected to the oscillator and having a tuning capacitance responsive to a tuning signal to alter a frequency of the oscillator signal;

a selectable capacitance device connected to the oscillator and responsive to a control signal such that the selectable capacitance device has a first capacitance at a control signal first value and a second capacitance at a control signal second value; and

a capacitance controller configured to only select either the first capacitance or the second capacitance by providing the control signal that has the control signal first value to select the first capacitance and having the control signal second value to select the second capacitance.

2. The PLL apparatus of claim 1, wherein the capacitance controller is configured to compensate for a shift in a relationship between the tuning signal and the frequency by changing the control signal from the control signal first value to the control signal second value.

3. The PLL apparatus of claim 2, wherein a shift in the relationship between the tuning signal and the frequency is due to at least one of a temperature change, a supply voltage change, a change in component age, a change in physical configuration of a circuit, a change in physical configuration of a housing, and a change in physical configuration of a device.

4. The PLL apparatus of claim 1, wherein the selectable capacitance device has a selectable capacitance device capacitance non-linearly related to bias voltage and defined by a ratio to voltage function where a capacitance change to voltage change ratio (Δ

C/Δ

V) is a function of bias voltage, the first control signal value and the second control signal value selected to establish bias voltages in regions of the (Δ

C/Δ

V) ratio to voltage function having lower (Δ

C/Δ

V) ratio to bias voltage ratios ((Δ

C/Δ

V)/V) than at least one other region of the (Δ

C/Δ

V) ratio to voltage function.

5. The PLL apparatus of claim 4, wherein the selectable capacitance device capacitance is constant for bias voltages in the regions.

6. The PLL apparatus of claim 1, wherein the selectable capacitance device includes at least two variable capacitance elements.

7. The PLL apparatus of claim 1, further comprising a voltage rate of change limiting device (VRCLD) configured to limit a rate of change in the voltage that is applied to a control input at the selectable capacitance device.

8. The PLL apparatus of claim 7, wherein the VRCLD comprises a charge pump and a filter.

9. The PLL apparatus of claim 7, wherein the VRCLD comprises a current limiting element limiting a current between the capacitance controller and the selectable capacitance device.

10. The PLL apparatus of claim 9, wherein the VRCLD comprises a filter.

11. The PLL apparatus of claim 9, wherein the VRCLD comprises a switchable current source.

12. The PLL apparatus of claim 1, wherein the selectable capacitance device is a first selectable capacitance device having a first component capacitance responsive to a first control signal, the apparatus further comprising a second selectable capacitance device having a second component capacitance responsive to a second control signal and wherein the capacitance controller is further configured to simultaneously provide the first control signal and the second control signal, the first control signal setting the first component capacitance to either the first capacitance or the second capacitance and the second control signal setting the second component capacitance to either a third capacitance or a fourth capacitance.

13. A method of shifting a tuning range of a phase locked loop apparatus comprising an oscillator generating an oscillator signal having a frequency based on a tuning signal, the method comprising:

selecting only either a first capacitance or a second capacitance of a selectable capacitance device by providing a control signal that has a control signal first value to select the first capacitance and having a control signal second value to select the second capacitance, the first capacitance at least partially establishing a first relationship between the frequency and the tuning signal and the second capacitance at least partially establishing a second relationship between the frequency and the tuning signal.

14. The method of claim 13, further comprising:

determining a difference between a tuning signal voltage and a threshold voltage;

determining a desired selectable capacitance based on the difference;

generating the control signal in accordance with the desired selectable capacitance to set the selectable capacitance device to either the first capacitance or the second capacitance.

15. The method of claim 14, wherein the determining the desired selectable capacitance comprises selecting the desired selectable capacitance to increase the difference between the threshold voltage and the tuning signal voltage for a particular frequency of the oscillator signal.

16. The method of claim 15, wherein the determining the difference comprises comparing the tuning signal voltage to a minimum voltage and to a maximum voltage;

and wherein the desired selectable capacitance maintains an oscillator output signal frequency range corresponding to a tuning signal input range between the minimum voltage and maximum voltage.

17. The method of claim 13, further comprising:

detecting a shift in a relationship between the tuning signal and the frequency;

changing the control signal from the control signal first value to the control signal second value to at least partially compensate for the shift in an opposite direction to direction of the shift.

18. The method of claim 17, wherein a shift in the relationship between the tuning signal and the frequency is due to at least one of a temperature change, a supply voltage change, a change in component age, a change in physical configuration of a circuit, a change in physical configuration of a housing, and a change in physical configuration of a device.

19. The method of claim 13, wherein the selectable capacitance device includes at least two variable capacitance elements.

20. The method of claim 13, further comprising:

limiting a rate of change in the voltage that is applied at a control input at the selectable capacitance device.

21. The method of claim 20, wherein limiting the rate of change in the voltage comprises filtering of the control signal.

22. The method of claim 20, wherein limiting the rate of change in the voltage comprises managing a current of the control signal.

23. A method of claim 13, further comprising:

simultaneously providing a first control signal to a first selectable capacitance device connected in parallel with the oscillator generating the oscillator signal and a second control signal to a second selectable capacitance device connected in parallel with the oscillator to set a selectable capacitance at least partially establishing a relationship between the frequency and the tuning signal.

24. A phase locked loop (PLL) apparatus comprising:

an oscillator means for generating an oscillator signal;

a variable capacitance device means for altering a frequency of the oscillator signal, the variable capacitance device means connected to the oscillator means and having a tuning capacitance responsive to a tuning signal to alter the frequency of the oscillator signal;

a selectable capacitance device means for selecting a capacitance, the selectable capacitance device means connected to the oscillator means and responsive to a control signal such that the selectable capacitance device means has a first capacitance at a control signal first value and a second capacitance at a control signal second value; and

a capacitance controller means for controlling the capacitance by only selecting either the first capacitance or the second capacitance by providing the control signal that has the control signal first value to select the first capacitance and having the control signal second value to select the second capacitance.

25. The PLL apparatus of claim 24, wherein the capacitance controller means is further for compensating for a shift in a relationship between the tuning signal and the frequency by changing the control signal from the control signal first value to the control signal second value.

26. The PLL apparatus of claim 25, wherein a shift in the relationship between the tuning signal and the frequency is due to at least one of a temperature change, a supply voltage change, a change in component age, a change in physical configuration of a circuit, a change in physical configuration of a housing, and a change in physical configuration of a device.

27. The PLL apparatus of claim 24, wherein the selectable capacitance device means has a selectable capacitance device capacitance non-linearly related to bias voltage and defined by a ratio to voltage function where a capacitance change to voltage change ratio (Δ

C/Δ

V) is a function of bias voltage, the first control signal value and the second control signal value selected to establish bias voltages in regions of the (Δ

C/Δ

V) ratio to voltage function having lower (Δ

C/Δ

V) ratio to bias voltage ratios ((Δ

C/Δ

V)/V) than at least one other region of the (Δ

C/Δ

V) ratio to voltage function.

28. The PLL apparatus of claim 27, wherein the selectable capacitance device capacitance is constant for bias voltages in the regions.

29. The PLL apparatus of claim 24, wherein the selectable capacitance device means includes at least two variable capacitance element means.

30. The PLL apparatus of claim 24, further comprising a voltage rate of change limiting device (VRCLD) means for limiting a rate of change in the voltage that is applied to a control input at the selectable capacitance device means.

31. The PLL apparatus of claim 30, wherein the VRCLD means comprises a current limiting element means for limiting a current between the capacitance controller means and the selectable capacitance device means.

32. The PLL apparatus of claim 30, wherein the VRCLD means comprises a filter means.

33. The PLL apparatus of claim 30, wherein the VRCLD means comprises a charge pump means.

34. The PLL apparatus of claim 24, wherein the selectable capacitance device means is a first selectable capacitance device means having a first component capacitance responsive to a first control signal, the apparatus further comprising a second selectable capacitance device means having a second component capacitance responsive to a second control signal and wherein the capacitance controller means is for simultaneously providing the first control signal and the second control signal, the first control signal setting the first component capacitance to either the first capacitance or the second capacitance and the second control signal setting the second component capacitance to either a third capacitance or a fourth capacitance.

35. A computer-readable medium encoded with computer-executable instructions, the execution of the computer-executable instructions for shifting a tuning range of a phase locked loop apparatus comprising an oscillator generating an oscillator signal having a frequency based on a tuning signal, the execution of the computer-executable instructions for:

selecting only either a first capacitance or a second capacitance of a selectable capacitance device by providing a control signal that has a control signal first value to select the first capacitance and having a control signal second value to select the second capacitance, the first capacitance at least partially establishing a first relationship between the frequency and the tuning signal and the second capacitance at least partially establishing a second relationship between the frequency and the tuning signal.

36. The computer-readable medium of claim 35, further comprising computer-executable instructions for:

determining a difference between a tuning signal voltage and a threshold voltage;

determining a desired selectable capacitance based on the difference;

generating the control signal in accordance with the desired selectable capacitance to set the selectable capacitance device to either the first capacitance or the second capacitance.

37. The computer-readable medium of claim 36, wherein the determining the desired selectable capacitance comprises selecting the desired selectable capacitance to increase the difference between the threshold voltage and the tuning signal voltage for a particular frequency of the oscillator signal.

38. The computer-readable medium of claim 37, wherein the determining the difference comprises comparing the tuning signal voltage to a minimum voltage and to a maximum voltage;

and wherein the desired selectable capacitance maintains an oscillator output signal frequency range corresponding to a tuning signal input range between the minimum voltage and maximum voltage.

39. The computer-readable medium of claim 35, further comprising computer-executable instructions for:

detecting a shift in a relationship between the tuning signal and the frequency;

changing the control signal from the control signal first value to the control signal second value to at least partially compensate for the shift in an opposite direction to direction of the shift.

40. The computer-readable medium of claim 39, wherein a shift in the relationship between the tuning signal and the frequency is due to at least one of a temperature change, a supply voltage change, a change in component age, a change in physical configuration of a circuit, a change in physical configuration of a housing, and a change in physical configuration of a device.

41. The computer-readable medium of claim 35, further comprising computer-executable instructions for:

limiting a rate of change in the voltage that is applied at a control input at the selectable capacitance device.

42. The computer-readable medium of claim 41, wherein limiting the rate of change in the voltage comprises managing a current of the control signal.

43. The computer-readable medium of claim 35, further comprising computer-executable instructions for:

simultaneously providing a first control signal to a first selectable capacitance device connected in parallel with the oscillator generating the oscillator signal and a second control signal to a second selectable capacitance device connected in parallel with the oscillator to set a selectable capacitance at least partially establishing a relationship between the frequency and the tuning signal.